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Background:

I am doing a re-design of an existing system moving from HC11 base with memory mapped I/O to an ARM Cortex-M3 with serial SPI/I2C I/O (opto-isolated inputs and relay outputs). I/O access will be via serial SPI or I2C to I/O expander chips (MCP23S17). 2 Chips per board for 32 I/O points each, and up to 4 boards can be stacked/interconnected via short ribbon cable for the SPI buss. The microprocessor board will be stacked on top of the main I/O board and have access to additional I/O boards via the SPI buss as mentioned above.

Question:

Is going this serial route, SPI to MCP23S17, going to be rock solid reliable in accessing the I/O points or will the serial nature just be too susceptible to noise and/or other related problems?

This is mission-critical control system running 24/7 7 days a week, polling the I/O say between 500Hz and 1kHz. In 20+ years with my current HC11 memory mapped design with the I/O being accessed over a 3ft 50pin ribbon cable, I have never had a single issue but I am concerned that moving to a serial SPI-based design could start causing all sorts of problems.

Would appreciate any of your thoughts and experience with this.

Thanks

Oh yea, forgot to mention that I want the SPI buss speed to be around 2MHz, so not all that fast but also not slow.

Background:

I am doing a re-design of an existing system moving from HC11 base with memory mapped I/O to an ARM Cortex-M3 with serial SPI/I2C I/O (opto-isolated inputs and relay outputs). I/O access will be via serial SPI or I2C to I/O expander chips (MCP23S17). 2 Chips per board for 32 I/O points each, and up to 4 boards can be stacked/interconnected via short ribbon cable for the SPI buss. The microprocessor board will be stacked on top of the main I/O board and have access to additional I/O boards via the SPI buss as mentioned above.

Question:

Is going this serial route, SPI to MCP23S17, going to be rock solid reliable in accessing the I/O points or will the serial nature just be too susceptible to noise and/or other related problems?

This is mission-critical control system running 24/7 7 days a week, polling the I/O say between 500Hz and 1kHz. I want the SPI bus speed to be around 2MHz, so not all that fast but also not slow.

In 20+ years with my current HC11 memory mapped design with the I/O being accessed over a 3ft 50pin ribbon cable, I have never had a single issue but I am concerned that moving to a serial SPI-based design could start causing all sorts of problems.

Would appreciate any of your thoughts and experience with this.

Background: I am doing a re-design of an existing system moving from HC11 base with memory mapped I/O to an ARM cortex M3 with serial SPI/I2C I/O (opto isolated inputs and relay outputs). I/O access will be via serial SPI or I2C to I/O expander chips (MCP23s17). 2 Chips per board for 32 I/O points each, and up to 4 boards can be stacked/interconnected via short ribbon cable for the SPI buss. The microprocessor board will be stacked on top of the main I/O board and have access to additional I/O boards via the SPI buss as mentioned above.

Question: Is going this serial route, SPI to MCP23S17, going to be rock solid reliable in accessing the I/O points or will the serial nature just be too susceptible to noise and/or other related problems. This is mission critical control system running 24/7 7 days a week polling the I/O say between 500hz and 1Khz. In 20+ years with my current HC11 memory mapped design with the I/O being accessed over a 3ft 50pin ribbon cable I have never had a single issue but I am concerned that moving to a serial SPI based design could start causing all sorts of problems.

Would appreciate any of your thoughts and experience with this.

Thanks

Oh yea, forgot to mention that I want the SPI buss speed to be around 2Mhz, so not all that fast but also not slow.

Background:

I am doing a re-design of an existing system moving from HC11 base with memory mapped I/O to an ARM Cortex-M3 with serial SPI/I2C I/O (opto-isolated inputs and relay outputs). I/O access will be via serial SPI or I2C to I/O expander chips (MCP23S17). 2 Chips per board for 32 I/O points each, and up to 4 boards can be stacked/interconnected via short ribbon cable for the SPI buss. The microprocessor board will be stacked on top of the main I/O board and have access to additional I/O boards via the SPI buss as mentioned above.

Question:

Is going this serial route, SPI to MCP23S17, going to be rock solid reliable in accessing the I/O points or will the serial nature just be too susceptible to noise and/or other related problems?

This is mission-critical control system running 24/7 7 days a week, polling the I/O say between 500Hz and 1kHz. In 20+ years with my current HC11 memory mapped design with the I/O being accessed over a 3ft 50pin ribbon cable, I have never had a single issue but I am concerned that moving to a serial SPI-based design could start causing all sorts of problems.

Would appreciate any of your thoughts and experience with this.

Thanks

Oh yea, forgot to mention that I want the SPI buss speed to be around 2MHz, so not all that fast but also not slow.

Background: I am doing a re-design of an existing system moving from HC11 base with memory mapped I/O to an ARM cortex M3 with serial SPI/I2C I/O (opto isolated inputs and relay outputs). I/O access will be via serial SPI or I2C to I/O expander chips (MCP23s17). 2 Chips per board for 32 I/O points each, and up to 4 boards can be stacked/interconnected via short ribbon cable for the SPI buss. The microprocessor board will be stacked on top of the main I/O board and have access to additional I/O boards via the SPI buss as mentioned above.

Question: Is going this serial route, SPI to MCP23S17, going to be rock solid reliable in accessing the I/O points or will the serial nature just be too susceptible to noise and/or other related problems. This is mission critical control system running 24/7 7 days a week polling the I/O say between 500hz and 1Khz. In 20+ years with my current HC11 memory mapped design with the I/O be accessed over a 3ft 50pin ribbon cable I have never had a single issue but I am concerned that moving to a serial SPI based design could start causing all sorts of problems.

Would appreciate any of your thoughts and experience with this.

Thanks

Oh yea, forgot to mention that I want the SPI buss speed to be around 2Mhz, so not all that fast but also not slow.

Background: I am doing a re-design of an existing system moving from HC11 base with memory mapped I/O to an ARM cortex M3 with serial SPI/I2C I/O (opto isolated inputs and relay outputs). I/O access will be via serial SPI or I2C to I/O expander chips (MCP23s17). 2 Chips per board for 32 I/O points each, and up to 4 boards can be stacked/interconnected via short ribbon cable for the SPI buss. The microprocessor board will be stacked on top of the main I/O board and have access to additional I/O boards via the SPI buss as mentioned above.

Question: Is going this serial route, SPI to MCP23S17, going to be rock solid reliable in accessing the I/O points or will the serial nature just be too susceptible to noise and/or other related problems. This is mission critical control system running 24/7 7 days a week polling the I/O say between 500hz and 1Khz. In 20+ years with my current HC11 memory mapped design with the I/O being accessed over a 3ft 50pin ribbon cable I have never had a single issue but I am concerned that moving to a serial SPI based design could start causing all sorts of problems.

Would appreciate any of your thoughts and experience with this.

Thanks

Oh yea, forgot to mention that I want the SPI buss speed to be around 2Mhz, so not all that fast but also not slow.