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Tom Carpenter
Tom Carpenter
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module up_down_counter( input clock, input reset, input load, input up_down, //up_down = 1'b1,upcounter; up_down=1'b0,down_counter input [3:0] data, output [3:0] counter );

reg [3:0] counter_reg;

always@(posedge clock or posedge reset) begin

module up_down_counter(
  input clock,
  input reset,
  input load,
  input up_down,            //up_down = 1'b1,upcounter; up_down=1'b0,down_counter
  input [3:0] data,
  output [3:0] counter
  );
  
  reg [3:0] counter_reg;  
  
  
  always@(posedge clock or posedge reset)
  begin
        
    if(reset == 1'b1)
      begin
      counter_reg <= 4'b0000;                
      end      
    else
       begin      
        if (up_down == 1'b1)
              begin
             if(load == 1'b1)
                begin
                counter_reg <= data;
                end
             else 
                begin
            counter_reg <= counter_reg + 4'b0001;
            end      
                      
          end    
     
        else 
              begin
             if(load == 1'b1)
               begin
               counter_reg <= data;
               end
             else 
               begin
           counter_reg <= counter_reg - 4'b0001; 
           end       
          end        
        end
 end  
  
  
  assign counter = counter_reg; 
  
  endmodule

end

assign counter = counter_reg;

endmodule

my Test Bench:

module tb_up_down_counter;

reg clock; reg reset; wire [3:0] counter; reg up_down; reg load; reg [3:0] data;

up_down_counter dut( .clock(clock), .reset(reset), .load(load), .data(data), .up_down(up_down), .counter(counter) );

initial begin clock = 1'b0; forever #50 clock = ~clock; end

module tb_up_down_counter;

  reg clock;
  reg reset;
  wire [3:0] counter; 
  reg up_down;
  reg load;
  reg [3:0] data;   
  
  up_down_counter dut(
  .clock(clock),
  .reset(reset),
  .load(load),
  .data(data),
  .up_down(up_down),
  .counter(counter)
  );
  
  initial
    begin
    clock = 1'b0;
    forever #50 clock = ~clock;
    end       
  
    
    initial 
     begin
    reset <= 1'b0;
    load  <= 1'b0;
    up_down <= 1'b0;    
    
    
    data <= 4'd0; 
    
    repeat(5)
    @(posedge clock);     
    reset <= 1'b1;
    
    repeat(5)
    @(posedge clock); 
     reset <= 1'b0; 
     
     repeat(10)
    @(posedge clock);
    up_down <= 1'b1;
    
    repeat(5)
    @(posedge clock);
    load <= 1'b1;    
    
    repeat(10)
    @(posedge clock);
    data <= 4'd3;    
        
   
    repeat(5)
    @(posedge clock);
    up_down <= 1'b0;
    
    repeat(5)
    @(posedge clock);
    load <= 1'b0;
    
    repeat(5)
    @(posedge clock);
    load <= 1'b1; 
    
    repeat(10)
    @(posedge clock);
    data <= 4'd5;   
    
    repeat(5)
    @(posedge clock);
    up_down <= 1'b1;   
    
    repeat(5)
    @(posedge clock);
    reset <= 1'b1;
    
    repeat(10)
    @(posedge clock);
    reset <= 1'b0;    
    
     repeat(10)
    @(posedge clock);
    load <= 1'b1;
    
    repeat(10)
    @(posedge clock);
    data <= 4'd8;
    
    repeat(10)
    @(posedge clock);
    data <= 4'd15;
    
    repeat(10)
    @(posedge clock);
    data <= 4'd12;
    
      
    
    #5000 $finish;
    end


 initial
 begin
 $shm_open("waves.shm");
 $shm_probe(tb_up_down_counter,"AC");
 end
 
 
 
 
 endmodule

initial begin $shm_open("waves.shm"); $shm_probe(tb_up_down_counter,"AC"); end

endmodule

module up_down_counter( input clock, input reset, input load, input up_down, //up_down = 1'b1,upcounter; up_down=1'b0,down_counter input [3:0] data, output [3:0] counter );

reg [3:0] counter_reg;

always@(posedge clock or posedge reset) begin

if(reset == 1'b1)
  begin
  counter_reg <= 4'b0000;                
  end      
else
   begin      
    if (up_down == 1'b1)
          begin
         if(load == 1'b1)
            begin
            counter_reg <= data;
            end
         else 
            begin
        counter_reg <= counter_reg + 4'b0001;
        end      
                  
      end    
 
    else 
          begin
         if(load == 1'b1)
           begin
           counter_reg <= data;
           end
         else 
           begin
       counter_reg <= counter_reg - 4'b0001; 
       end       
      end        
    end

end

assign counter = counter_reg;

endmodule

my Test Bench:

module tb_up_down_counter;

reg clock; reg reset; wire [3:0] counter; reg up_down; reg load; reg [3:0] data;

up_down_counter dut( .clock(clock), .reset(reset), .load(load), .data(data), .up_down(up_down), .counter(counter) );

initial begin clock = 1'b0; forever #50 clock = ~clock; end

initial 
 begin
reset <= 1'b0;
load  <= 1'b0;
up_down <= 1'b0;    


data <= 4'd0; 

repeat(5)
@(posedge clock);     
reset <= 1'b1;

repeat(5)
@(posedge clock); 
 reset <= 1'b0; 
 
 repeat(10)
@(posedge clock);
up_down <= 1'b1;

repeat(5)
@(posedge clock);
load <= 1'b1;    

repeat(10)
@(posedge clock);
data <= 4'd3;    
    

repeat(5)
@(posedge clock);
up_down <= 1'b0;

repeat(5)
@(posedge clock);
load <= 1'b0;

repeat(5)
@(posedge clock);
load <= 1'b1; 

repeat(10)
@(posedge clock);
data <= 4'd5;   

repeat(5)
@(posedge clock);
up_down <= 1'b1;   

repeat(5)
@(posedge clock);
reset <= 1'b1;

repeat(10)
@(posedge clock);
reset <= 1'b0;    

 repeat(10)
@(posedge clock);
load <= 1'b1;

repeat(10)
@(posedge clock);
data <= 4'd8;

repeat(10)
@(posedge clock);
data <= 4'd15;

repeat(10)
@(posedge clock);
data <= 4'd12;

  

#5000 $finish;
end

initial begin $shm_open("waves.shm"); $shm_probe(tb_up_down_counter,"AC"); end

endmodule

module up_down_counter(
  input clock,
  input reset,
  input load,
  input up_down,            //up_down = 1'b1,upcounter; up_down=1'b0,down_counter
  input [3:0] data,
  output [3:0] counter
  );
  
  reg [3:0] counter_reg;  
  
  
  always@(posedge clock or posedge reset)
  begin
        
    if(reset == 1'b1)
      begin
      counter_reg <= 4'b0000;                
      end      
    else
       begin      
        if (up_down == 1'b1)
              begin
             if(load == 1'b1)
                begin
                counter_reg <= data;
                end
             else 
                begin
            counter_reg <= counter_reg + 4'b0001;
            end      
                      
          end    
     
        else 
              begin
             if(load == 1'b1)
               begin
               counter_reg <= data;
               end
             else 
               begin
           counter_reg <= counter_reg - 4'b0001; 
           end       
          end        
        end
 end  
  
  
  assign counter = counter_reg; 
  
  endmodule

my Test Bench:

module tb_up_down_counter;

  reg clock;
  reg reset;
  wire [3:0] counter; 
  reg up_down;
  reg load;
  reg [3:0] data;   
  
  up_down_counter dut(
  .clock(clock),
  .reset(reset),
  .load(load),
  .data(data),
  .up_down(up_down),
  .counter(counter)
  );
  
  initial
    begin
    clock = 1'b0;
    forever #50 clock = ~clock;
    end       
  
    
    initial 
     begin
    reset <= 1'b0;
    load  <= 1'b0;
    up_down <= 1'b0;    
    
    
    data <= 4'd0; 
    
    repeat(5)
    @(posedge clock);     
    reset <= 1'b1;
    
    repeat(5)
    @(posedge clock); 
     reset <= 1'b0; 
     
     repeat(10)
    @(posedge clock);
    up_down <= 1'b1;
    
    repeat(5)
    @(posedge clock);
    load <= 1'b1;    
    
    repeat(10)
    @(posedge clock);
    data <= 4'd3;    
        
   
    repeat(5)
    @(posedge clock);
    up_down <= 1'b0;
    
    repeat(5)
    @(posedge clock);
    load <= 1'b0;
    
    repeat(5)
    @(posedge clock);
    load <= 1'b1; 
    
    repeat(10)
    @(posedge clock);
    data <= 4'd5;   
    
    repeat(5)
    @(posedge clock);
    up_down <= 1'b1;   
    
    repeat(5)
    @(posedge clock);
    reset <= 1'b1;
    
    repeat(10)
    @(posedge clock);
    reset <= 1'b0;    
    
     repeat(10)
    @(posedge clock);
    load <= 1'b1;
    
    repeat(10)
    @(posedge clock);
    data <= 4'd8;
    
    repeat(10)
    @(posedge clock);
    data <= 4'd15;
    
    repeat(10)
    @(posedge clock);
    data <= 4'd12;
    
      
    
    #5000 $finish;
    end


 initial
 begin
 $shm_open("waves.shm");
 $shm_probe(tb_up_down_counter,"AC");
 end
 
 
 
 
 endmodule
Clarification.
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TonyM
TonyM
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Synchronising the signals of TestVerilog test bench with rtlRTL clock

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Dig_Verif_bee
Dig_Verif_bee
  • 43
  • 1
  • 9

Synchronising the signals of Test bench with rtl clock

I have been given an interesting assignment. My task was to design a 4 bit up_down counter which has two controlling signals, up_down and load. The up_down decides weather the counter should be up-counting or down-counting(up_down=1'b1 up-counting and up_down=1'b0 down-counting). The load signal is to load the 4 bit data into the counter. I was able to design and verify the code in rtl and test bench.

But now I am notified to make sure my input driving signals from test bench arrive after the posedge of the clock in RTL. That means my load and up_down signals should arrive after the positive clock edge of the RTL clock. Please find my rtl and testbench. I am told to do something in testbench as in write a logic in Test bench to make sure my signals arrive later the posedge. I would need some help on this. Please do respond.

My RTL code:

module up_down_counter( input clock, input reset, input load, input up_down, //up_down = 1'b1,upcounter; up_down=1'b0,down_counter input [3:0] data, output [3:0] counter );

reg [3:0] counter_reg;

always@(posedge clock or posedge reset) begin

if(reset == 1'b1)
  begin
  counter_reg <= 4'b0000;                
  end      
else
   begin      
    if (up_down == 1'b1)
          begin
         if(load == 1'b1)
            begin
            counter_reg <= data;
            end
         else 
            begin
        counter_reg <= counter_reg + 4'b0001;
        end      
                  
      end    
 
    else 
          begin
         if(load == 1'b1)
           begin
           counter_reg <= data;
           end
         else 
           begin
       counter_reg <= counter_reg - 4'b0001; 
       end       
      end        
    end

end

assign counter = counter_reg;

endmodule

my Test Bench:

module tb_up_down_counter;

reg clock; reg reset; wire [3:0] counter; reg up_down; reg load; reg [3:0] data;

up_down_counter dut( .clock(clock), .reset(reset), .load(load), .data(data), .up_down(up_down), .counter(counter) );

initial begin clock = 1'b0; forever #50 clock = ~clock; end

initial 
 begin
reset <= 1'b0;
load  <= 1'b0;
up_down <= 1'b0;    


data <= 4'd0; 

repeat(5)
@(posedge clock);     
reset <= 1'b1;

repeat(5)
@(posedge clock); 
 reset <= 1'b0; 
 
 repeat(10)
@(posedge clock);
up_down <= 1'b1;

repeat(5)
@(posedge clock);
load <= 1'b1;    

repeat(10)
@(posedge clock);
data <= 4'd3;    
    

repeat(5)
@(posedge clock);
up_down <= 1'b0;

repeat(5)
@(posedge clock);
load <= 1'b0;

repeat(5)
@(posedge clock);
load <= 1'b1; 

repeat(10)
@(posedge clock);
data <= 4'd5;   

repeat(5)
@(posedge clock);
up_down <= 1'b1;   

repeat(5)
@(posedge clock);
reset <= 1'b1;

repeat(10)
@(posedge clock);
reset <= 1'b0;    

 repeat(10)
@(posedge clock);
load <= 1'b1;

repeat(10)
@(posedge clock);
data <= 4'd8;

repeat(10)
@(posedge clock);
data <= 4'd15;

repeat(10)
@(posedge clock);
data <= 4'd12;

  

#5000 $finish;
end

initial begin $shm_open("waves.shm"); $shm_probe(tb_up_down_counter,"AC"); end

endmodule