Timeline for Synchronising signals of Verilog test bench with RTL clock
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jan 24, 2018 at 14:08 | vote | accept | Dig_Verif_bee | ||
| Jan 24, 2018 at 13:03 | comment | added | Dig_Verif_bee | Thank you. You were absolutely right. The test bench with your approach worked perfectly and now I am told to do the self checking function in test bench. Starting with this now. Will have look at your link.Thanks once again. | |
| Jan 24, 2018 at 10:30 | comment | added | Oldfart | You make a clock in your test bench which always runs. Then in your initial section you do @(posedge clock ) load <= '1'; If you look here: www.verilog.pro you find plenty of examples of not only code but self-checking test benches too. The latter are often left out on other Verilog learning sites. | |
| Jan 24, 2018 at 9:38 | comment | added | Dig_Verif_bee | Hello oldfart, could you please clear few things for me. I have used the same names in my tb as load and count_up as in rtl and will connect them via .load(load),.count_up(count_up). but if I write the conditional block where if(reset) load<= 1'b0 else load<=load?? there wont be any input value given to load in tb at all right? | |
| Jan 24, 2018 at 9:24 | comment | added | Dig_Verif_bee | Thank you for your comments. Really helpful. I will try to do the suggested way and get back to you with the results. Kind regards | |
| Jan 23, 2018 at 16:57 | history | answered | Oldfart | CC BY-SA 3.0 |