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Transmission line effects create false transitions from ringing when the Return Loss or Impedance mismatch occurs from time delays greater than the rise time.

Generally 74HCT logic is rated with 50pF and Vol rated at 4mA for some Vol like 0.4Vmax with an input threshold of 2 TTL diode drops or 1.4~1.5V and may have a rise time of 15ns @ 50pF over all temps but best case may be faster.

Using impedance of the back plane tracks to ground, you can compute the track capacitance and also compute the time delay and decide what is worse.

  • 1) High impedance stripline with lower capacitance but higher inductance and high mismatch ?
  • 2) Low impedance ( 50~100 Ohms) with high capacitance going at 2/3c velocity with matched terminations..

Use a track capacitance , impedance, prop delay calculator and use a 74HCTxx driver impedance of 50 to 100 Ohms with an RC rise time to estimate if rise time is > time delay.

If you do need termination it still becomes a tradeoff but will likely be an R pair network resistor DIP or SIP or SOIC that biases to 1.5V with some impedance unless you choose 74ACxx or other family.

As your backplane is edge sensitive such as going to counters , latches, you will want to compute noise margin in the clock drivers.

I suspect the rise time is too slow, but they don't give best case specs.

Transmission line effects create false transitions from ringing when the Return Loss or Impedance mismatch occurs from time delays greater than the rise time.

Generally 74HCT logic is rated with 50pF and Vol rated at 4mA for some Vol like 0.4Vmax with an input threshold of 2 TTL diode drops or 1.4~1.5V and may have a rise time of 15ns @ 50pF over all temps but best case may be faster.

Using impedance of the back plane tracks to ground, you can compute the track capacitance and also compute the time delay and decide what is worse.

  • 1) High impedance stripline with lower capacitance but higher inductance and high mismatch ?
  • 2) Low impedance ( 50~100 Ohms) with high capacitance going at 2/3c velocity with matched terminations..

Use a track capacitance , impedance, prop delay calculator and use a 74HCTxx driver impedance of 50 to 100 Ohms with an RC rise time to estimate if rise time is > time delay.

If you do need termination it still becomes a tradeoff but will likely be an R pair network resistor DIP or SIP or SOIC that biases to 1.5V with some impedance unless you choose 74ACxx or other family.

Transmission line effects create false transitions from ringing when the Return Loss or Impedance mismatch occurs from time delays greater than the rise time.

Generally 74HCT logic is rated with 50pF and Vol rated at 4mA for some Vol like 0.4Vmax with an input threshold of 2 TTL diode drops or 1.4~1.5V and may have a rise time of 15ns @ 50pF over all temps but best case may be faster.

Using impedance of the back plane tracks to ground, you can compute the track capacitance and also compute the time delay and decide what is worse.

  • 1) High impedance stripline with lower capacitance but higher inductance and high mismatch ?
  • 2) Low impedance ( 50~100 Ohms) with high capacitance going at 2/3c velocity with matched terminations..

Use a track capacitance , impedance, prop delay calculator and use a 74HCTxx driver impedance of 50 to 100 Ohms with an RC rise time to estimate if rise time is > time delay.

If you do need termination it still becomes a tradeoff but will likely be an R pair network resistor DIP or SIP or SOIC that biases to 1.5V with some impedance unless you choose 74ACxx or other family.

As your backplane is edge sensitive such as going to counters , latches, you will want to compute noise margin in the clock drivers.

I suspect the rise time is too slow, but they don't give best case specs.

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Transmission line effects create false transitions from ringing when the Return Loss or Impedance mismatch occurs from time delays greater than the rise time.

Generally 74HCT logic is rated with 50pF and Vol rated at 4mA for some Vol like 0.4Vmax with an input threshold of 2 TTL diode drops or 1.4~1.5V and may have a rise time of 15ns @ 50pF over all temps but best case may be faster.

Using impedance of the back plane tracks to ground, you can compute the track capacitance and also compute the time delay and decide what is worse.

  • 1) High impedance stripline with lower capacitance but higher inductance and high mismatch ?
  • 2) Low impedance ( 50~100 Ohms) with high capacitance going at 2/3c velocity with matched terminations..

Use a track capacitance , impedance, prop delay calculator and use a 74HCTxx driver impedance of 50 to 100 Ohms with an RC rise time to estimate if rise time is > time delay.

If you do need termination it still becomes a tradeoff but will likely be an R pair network resistor DIP or SIP or SOIC that biases to 1.5V with some impedance unless you choose 74ACxx or other family.