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Feb 27, 2018 at 1:17 history tweeted twitter.com/StackElectronix/status/968294099362242561
Feb 26, 2018 at 21:00 history reopened lucenzo97
Bence Kaulics
Dave Tweed
Feb 26, 2018 at 18:34 review Reopen votes
Feb 26, 2018 at 21:00
Feb 26, 2018 at 12:28 history closed Andy aka
Voltage Spike
Finbarr
user105652
Daniel Grillo
Needs details or clarity
Feb 23, 2018 at 4:05 comment added user105652 Why is C1 present when you have a bipolar power supply and Q1 is referenced to ground?
Feb 22, 2018 at 18:17 vote accept lucenzo97
Feb 22, 2018 at 18:17 vote accept lucenzo97
Feb 22, 2018 at 18:17
Feb 21, 2018 at 16:37 comment added lucenzo97 @G36 Okay. So, isn't said that 90° of phase margin would be perfect value for stability? And as we approach closed-loop gain of unity we also approach 90° of phase margin?
Feb 21, 2018 at 16:24 comment added G36 The small the closed loop gain is the more prone to the oscillation the circuit will be. electronics.stackexchange.com/questions/45064/… read Lvw post. And haven't we already discussed this? When you build the amplifier based on my schematic with unity gain, the circuit oscillates like hell. But increasing the gain to 11 stop the oscillations. Do you remember this?
Feb 21, 2018 at 12:26 answer added Andy aka timeline score: 2
Feb 21, 2018 at 4:47 answer added τεκ timeline score: 2
Feb 21, 2018 at 0:44 answer added jonk timeline score: 3
Feb 20, 2018 at 22:43 answer added Daniele Tampieri timeline score: 7
Feb 20, 2018 at 22:09 comment added jonk @Keno Please work out and compute what you get for the voltage at the junction of \$R_1\$ and \$R_2\$. What is the Thevenin voltage there and what is the Thevenin resistance there? Provide your equations and approach. Then examine your \$Q_3\$ and \$R_{E_3}\$ design and tell me what you think this should be doing. Not what it is doing. But what, in theory, it should do.
Feb 20, 2018 at 22:00 comment added lucas92 Did you try to simulate the circuit in LTSpice? Anyway, you should look at the way you make the current bias for Q1 and Q2 : I expect a current mirror feeding the circuit but all I see is a transistor polarized with a voltage divider. The rest looks pretty much standard to me (i.e. the feedback network going through the comparator).
Feb 20, 2018 at 21:37 review Close votes
Feb 26, 2018 at 12:28
Feb 20, 2018 at 21:25 comment added lucenzo97 @AlmostDone Okay, with that being said, I still doubt that any things regarding to small signal or AC is going to be different than as it is now (the problems that I have described)...
Feb 20, 2018 at 21:22 comment added lucenzo97 @Andyaka Thank you for your notice; I have just edited it.
Feb 20, 2018 at 21:22 history edited lucenzo97 CC BY-SA 3.0
added 63 characters in body
Feb 20, 2018 at 21:18 comment added Andy aka Loop gain is what it is, what you are referring to is the closed loop gain. Please fix.
Feb 20, 2018 at 21:07 comment added AlmostDone Edit: ...the -V supply.
Feb 20, 2018 at 21:07 comment added AlmostDone I believe Q3 is not fully biased. Calculate the drop you need across RE3 for 2 mA, add ~.6 V to that, and that's what you need between Q3 base and the V supply.
Feb 20, 2018 at 20:54 comment added lucenzo97 @AlmostDone Litle bit less - around 1.5 mA; I don't know why exactly but currents are split equally between two collectors of Q1 and Q2.
Feb 20, 2018 at 20:27 comment added AlmostDone I'm looking at the D.C. conditions. Have you measured the voltage across RE3 to verify your diff pair has 2 mA flowing?
Feb 20, 2018 at 20:09 history edited Neil_UK CC BY-SA 3.0
fixed up your broken link
Feb 20, 2018 at 19:51 history asked lucenzo97 CC BY-SA 3.0