Timeline for how to place decoupling capacitors on a four-layer board for through-hole components?
Current License: CC BY-SA 3.0
15 events
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| Apr 25, 2018 at 15:44 | comment | added | DerStrom8 | @StefanWyss Interesting indeed. How might you account for hundreds of datasheets I've seen that specifically state that multiple bypass caps of different values are required? Perhaps the impedance spikes are assumed to not affect these devices? FPGAs are a major example of such requirements | |
| Apr 25, 2018 at 15:27 | comment | added | Stefan Wyss | @DerStrom8: I try to explain why it is not good to use multiple bypass caps with different values. You are right with the „V“ shape in the charts. But multiple „V“ at different frequencies in parallel do lead to the following problem: Each cap can be modeled as series R, L an parallel C. If you have multiple caps, the L of one cap also forms a parallel resonance circuit with the C of another one. This leads to regions between the „V“s where you have huge impedance (parallel resonance circuit) So your combined chart looks more like „v^v^v“. This is shown in some charts in the book i mentioned. | |
| Apr 25, 2018 at 11:03 | comment | added | DerStrom8 | I've edited my answer to direct the reader to these comments for more information, as well as to clarify that this is only what I've learned. This discussion has been very informative and I may have to look into this further. | |
| Apr 25, 2018 at 11:02 | history | edited | DerStrom8 | CC BY-SA 3.0 |
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| Apr 25, 2018 at 10:55 | comment | added | DerStrom8 | @StefanWyss Interesting. I do not agree with #1, but I can certainly see the remaining three being potentially accurate. Re. #1 it's often necessary to use multiple bypass caps of different values in order to decouple the supply from noise of different frequencies. If you look at the chart of a capacitor's ESL vs. edge speed you'll notice that it forms a distinct "V" shape, with the bottom of the "V" being the lowest ESL. If devices on your board are switching at different speeds it may be necessary to use multiple caps of different values in order to minimize ESL over the range of frequencies | |
| Apr 25, 2018 at 3:56 | comment | added | Stefan Wyss | @DerStrom8: Franz Joachim has written an excellent Book (EMV) about this topic (I don’t know if it is available in english). From there I learned: 1) If you use multiple decoupling caps for one pin, then all should have the same value. 2) The value of the caps is less important than the physical size of the cap. 3) For 2 layer PCB, always connect caps first. 4) For Multilayer, it can be better to connect plane first. | |
| Apr 24, 2018 at 23:14 | comment | added | DerStrom8 | @StefanWyss Yes, as I mentioned this has been a highly debated topic for decades, and I am open to the possibility that what I learned many years ago is wrong. Understanding of electronic circuits has changed quite a bit since then ;) | |
| Apr 24, 2018 at 19:54 | comment | added | Stefan Wyss | @DerStrom8: I do not agree that you should never connect IC pins directly to the plane. If the plane plus the vias have smaller impedance, it is better to connect to the plane than the cap. | |
| Apr 24, 2018 at 2:30 | history | edited | DerStrom8 | CC BY-SA 3.0 |
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| Apr 24, 2018 at 2:28 | comment | added | DerStrom8 | Also, depending on the via sizes and your board thickness, you may actually reduce inductance by connecting the capacitor pad directly to the IC VCC pin rather than dropping it through a via to a plane | |
| Apr 24, 2018 at 2:27 | comment | added | DerStrom8 | @luckybot This has been argued between engineers for decades and I am only repeating what I have learned over the years from numerous other professionals. Yes, I agree that minimized loop area and connection inductance are the most critical factors. The benefit of placing the decoupling capacitor as I have described it is that, depending on the specific design and from which direction current is supplied, if the current density is lower near the decoupling cap than near the IC pin it will be less effective against transients and voltage dips in the supply to the pin (less noise immunity). | |
| Apr 24, 2018 at 1:14 | comment | added | lucky bot | As the other answer states the only thing that matters is the loop area of the capacitor. The through hole device can still connect to the ground plane and why wouldn't it since you already have to make a hole to mount it. | |
| Apr 24, 2018 at 0:33 | vote | accept | EnTaroAdun | ||
| Apr 25, 2018 at 1:14 | |||||
| Apr 24, 2018 at 0:33 | comment | added | EnTaroAdun | Makes sense. Time to scrap my circuit in kicad and start over again o_O. | |
| Apr 23, 2018 at 21:45 | history | answered | DerStrom8 | CC BY-SA 3.0 |