As a general rule the following is true..
- U' = U NAND U
This can be built from one NAND gate.
- U OR V = U' NAND V' = (U NAND U) NAND (V NAND V)
This can be built from two 2-input NAND gates.
- U AND V = (U NAND V)' = (U NAND V) NAND (U NAND V)
This can be built from two 2-input NAND gates.
We can apply the above rules over and ove to the equation below.
(A'.B'.C'.x'+B.C.x)
A' = A NAND A
B' = B NAND B
C' = C NAND C
X' = X NAND X
D = A' NAND B' (intermediate signal)
E = C' NAND X' (intermediate signal)
D' = D NAND D (which is A'.B')
E' = E NAND E (which is C'.x')
F = D' NAND E' (intermediate signal)
F' = F NAND F (which is A'.B'.C'.x')
G = B NAND C (intermediate signal)
G' = G NAND G (which is B.C)
H = G' NAND X (intermediate signal)
H' = H NAND H (which is B.C.x)
I = F NAND H (which is A'.B'.C'.x'+B.C.x)
Expanding the whole thing gives...
A'.B'.C'.x'+B.C.x = F NAND H
A'.B'.C'.x'+B.C.x = (D' NAND E') NAND (G' NAND X)
A'.B'.C'.x'+B.C.x = ((D NAND D) NAND (E NAND E)) NAND ((G NAND G) NAND X)
A'.B'.C'.x'+B.C.x = (((A' NAND B') NAND (A' NAND B')) NAND ((C' NAND X') NAND (C' NAND X'))) NAND (((B NAND C) NAND (B NAND C)) NAND X)
A'.B'.C'.x'+B.C.x = ((((A NAND A) NAND (B NAND B)) NAND ((A NAND A) NAND (B NAND B))) NAND (((C NAND C) NAND (X NAND X)) NAND ((C NAND C) NAND (X NAND X)))) NAND (((B NAND C) NAND (B NAND C)) NAND X)
simulate this circuit – Schematic created using CircuitLab
