Timeline for SPI communication
Current License: CC BY-SA 3.0
13 events
| when toggle format | what | by | license | comment | |
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| Aug 22, 2012 at 13:15 | comment | added | stevenvh | @Chris - He's is slave mode, he can't help it! :-) | |
| Aug 22, 2012 at 13:04 | comment | added | Chris Stratton | Why do you keep clocking if you don't have data ready to send? | |
| Aug 22, 2012 at 11:45 | comment | added | BЈовић | Actually with TXFFIL :) TX FIFO can hold only 16 data words, which means you have to fill in when the TX FIFO level gets low. It takes some time to fill in this buffer, during which I see a garbage on the MISO line | |
| Aug 22, 2012 at 11:41 | comment | added | stevenvh | @BЈовић - Yes, you can set the interrupt level with the TXFFST bits, but would that help? If you would have data you would have written it to the FIFO already wouldn't you? | |
| Aug 22, 2012 at 11:34 | history | edited | stevenvh | CC BY-SA 3.0 |
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| Aug 22, 2012 at 11:32 | vote | accept | BЈовић | ||
| Aug 22, 2012 at 11:31 | comment | added | BЈовић | The data isn't there to send during the process of copying it to data buffer. So, I guess I should trigger TX FIFO interrupt not when the TX FIFO is empty, but when it gets low (2-4 words left to be sent). | |
| Aug 22, 2012 at 11:09 | history | edited | stevenvh | CC BY-SA 3.0 |
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| Aug 22, 2012 at 11:03 | comment | added | stevenvh | @BЈовић - I updated my answer. | |
| Aug 22, 2012 at 11:03 | history | edited | stevenvh | CC BY-SA 3.0 |
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| Aug 22, 2012 at 10:46 | comment | added | BЈовић | Bad wording. Under "full FIFO" I really meant "FIFO not empty". And what happens after it sends all data words from TX FIFO? Also, if I set data words to be 8-bit, is it sending 8-bits from SPIDAT? | |
| Aug 22, 2012 at 10:45 | history | edited | stevenvh | CC BY-SA 3.0 |
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| Aug 22, 2012 at 10:26 | history | answered | stevenvh | CC BY-SA 3.0 |