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I have created a Simulation of a 4 bit register in quartus. Each of the four D flip flops test fine by themselves, but when I test 4 of them connected together into a register, I get the "Error (suppressible): (vsim-3601) Iteration limit". If I assert the clear signal first (clearNMar, active low), I do not get the error and everything works fine...but I really should not HAVE to clear the register before using it. It should be "ok" for it to be undefined until the input signals are latched in. Below is the code...I will provide every component that I have used and its waveform building up to the register within reason. I am only allowed to post 8 links so I will not include the waveforms for the basic NOT, AND, NAND and OR gates. They definitely work though:

First, here is my 2 input AND gate:

--2 Input And Gate
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY REG_4_MAR_SAP_1AND_2 IS 
 PORT(
    GENERIC(In0, In1: IN STD_LOGIC;
    sizeOut0: INTEGER:=3OUT STD_LOGIC);
END AND_2;

ARCHITECTURE Dataflow_AND_2 of AND_2 IS
BEGIN
    Out0<=In0 AND In1;
END Dataflow_AND_2;

Next is the code for my 2 input NAND gate:

--LmNdataflow ismodel theof loada signal.2 input Itnand isgate

LIBRARY activeIEEE;
USE lowIEEE.STD_LOGIC_1164.ALL;
ENTITY soNAND_2 thereIS isPORT(
 a NOT gate In0, In1: IN STD_LOGIC;
leading into the E (enable)Out0: portOUT ofSTD_LOGIC);

END theNAND_2;


ARCHITECTURE DDataflow flipOF flopNAND_2 IS
BEGIN
    Out0<= In0 NAND In1;
END Dataflow;

Next is my 3 Input NAND gate code:

--clkMardataflow ismodel theof clocka for3 theinput registernand gate

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_3 --clearNMarIS isPORT(
 the clear for theIn0, registerIn1, whichIn2: connectsIN toSTD_LOGIC;
 the clear of theOut0: DOUT flipSTD_LOGIC);

END flops.NAND_3;


ARCHITECTURE Dataflow OF NAND_3 IS
BEGIN
    Out0<= (NOT(In0 NAND In1)) NAND In2;
END Dataflow;

Next is the code for my NOT gate:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.allALL;

ENTITY activeNOT_1 low.IS PORT(
    --DMarIn0: isIN theSTD_LOGIC;
 register input bus Out0: OUT STD_LOGIC);
END NOT_1;

ARCHITECTURE Dataflow_NOT_1 OF --QMarNOT_1 isIS
BEGIN
 the register output busOut0<= NOT In0;
END Dataflow_NOT_1;

Next is the code for my 3 input OR gate:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY OR_3 IS PORT(
    LmNIn0, ClkMarIn1, clearNMarIn2: IN STD_LOGIC;
    DMarOut0: IN STD_LOGIC_VECTOR(size DOWNTOOUT 0STD_LOGIC);
END OR_3;

ARCHITECTURE Dataflow_OR_3 OF QMar:OR_3 OUTIS
BEGIN
 STD_LOGIC_VECTOR   Out0<= In0 OR In1 OR In2;
END Dataflow_OR_3;

Next is my multiplexer. A diagram, the code, and the simulation is shown below. I apologize that I was not able to figure out how to get the signals (N1, N2...etc) onto the simulation:

enter image description here

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX_2_1 IS PORT(size 
 DOWNTO 0)  D0, D1, S: IN STD_LOGIC;
    Y: OUT STD_LOGIC);
 
END REG_4_MAR_SAP_1;MUX_2_1;

ARCHITECTURE Structural_REG_4_MAR_SAP_1Structural_MUX_2_1 OF REG_4_MAR_SAP_1MUX_2_1 IS
 
    SignalSIGNAL EsigN1, N2, N3, N4: STD_LOGIC;
 

    COMPONENT D_FF_W_ENABLE_CLEARNOT_1 PORT(
        D, E, ClearN, ClkIn0: IN STD_LOGIC;
        QOut0: BUFFEROUT STD_LOGIC);
    END COMPONENT;

    COMPONENT NOT_1AND_2 PORT(
        In0, In1: IN STD_LOGIC;
        Out0: OUT STD_LOGIC);
    END COMPONENT;
 

BEGIN
    COMPONENT OR_3 PORT(
    Reg4: FOR k  In0, In1, In2: IN sizeSTD_LOGIC;
 DOWNTO 0 GENERATE     Out0: OUT STD_LOGIC);
    END COMPONENT;

BEGIN
   FlipFlop U1: D_FF_W_ENABLE_CLEARNOT_1 PORT MAP(DMar(kS, N1);
    U2: AND_2 PORT MAP(D0, EsigN1, ClearNMarN2);
    U3: AND_2 PORT MAP(S, clkMarD1, QMar(k)N3);
    ENDU4: GENERATEAND_2 Reg4;
PORT MAP(D1, D0, N4);
    U1U5: NOT_1OR_3 PORT MAP(LmNN2, EsigN3, N4, Y);

END Structural_REG_4_MAR_SAP_1;Structural_MUX_2_1;

MUX

Here is the Diagram, Code and simulation of the D-flip flop code with a diagram to go with itwhich all works fine i think:

D-FlipFlop Diagram

Image belowDFlipSim

Diagram Finally, Here is the diagram, code and simulation of my register. I included the error simulation in which clearN(N means active low) is not asserted until a few clock cycles in, and the non-error simulation, when the clear is asserted at time "zero"

Sucessful D-flip flopenter image description hereenter image description here

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY REG_4_MAR_SAP_1 IS 

    GENERIC(
    size: INTEGER:=3);

    --LmN is the load signal.  It is active low so there is a NOT gate 
leading into the E (enable) port of the D flip flop
    --clkMar is the clock for the register
    --clearNMar is the clear for the register which connects to the clear of the D flip flops...all active low.
    --DMar is the register input bus
    --QMar is the register output bus

    PORT(
    LmN, ClkMar, clearNMar: IN STD_LOGIC;
    DMar: IN STD_LOGIC_VECTOR(size DOWNTO 0);
    QMar: OUT STD_LOGIC_VECTOR(size DOWNTO 0));

END REG_4_MAR_SAP_1;

ARCHITECTURE Structural_REG_4_MAR_SAP_1 OF REG_4_MAR_SAP_1 IS

    Signal Esig: STD_LOGIC;


    COMPONENT D_FF_W_ENABLE_CLEAR PORT(
        D, E, ClearN, Clk: IN STD_LOGIC;
        Q: BUFFER STD_LOGIC);
    END COMPONENT;

    COMPONENT NOT_1 PORT(
        In0: IN STD_LOGIC;
        Out0: OUT STD_LOGIC);
    END COMPONENT;


BEGIN

    Reg4: FOR k IN size DOWNTO 0 GENERATE
        FlipFlop: D_FF_W_ENABLE_CLEAR PORT MAP(DMar(k), Esig, ClearNMar, clkMar, QMar(k));
    END GENERATE Reg4;

    U1: NOT_1 PORT MAP(LmN, Esig);

END Structural_REG_4_MAR_SAP_1;

Here is the Error condition when clearNMar is first asserted at 3us: enter image description here

Here is the successful condition when clearNMar is asserted at time= 0us: enter image description here

I have created a Simulation of a 4 bit register in quartus. Each of the four D flip flops test fine by themselves, but when I test 4 of them connected together into a register, I get the "Error (suppressible): (vsim-3601) Iteration limit". If I assert the clear signal first (clearNMar, active low), I do not get the error and everything works fine...but I really should not HAVE to clear the register before using it. It should be "ok" for it to be undefined until the input signals are latched in. Below is the code:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY REG_4_MAR_SAP_1 IS 
 
    GENERIC(
    size: INTEGER:=3);

    --LmN is the load signal.  It is active low so there is a NOT gate 
leading into the E (enable) port of the D flip flop
    --clkMar is the clock for the register
    --clearNMar is the clear for the register which connects to the clear of the D flip flops...all active low.
    --DMar is the register input bus
    --QMar is the register output bus

    PORT(
    LmN, ClkMar, clearNMar: IN STD_LOGIC;
    DMar: IN STD_LOGIC_VECTOR(size DOWNTO 0);
    QMar: OUT STD_LOGIC_VECTOR(size DOWNTO 0));
 
END REG_4_MAR_SAP_1;

ARCHITECTURE Structural_REG_4_MAR_SAP_1 OF REG_4_MAR_SAP_1 IS
 
    Signal Esig: STD_LOGIC;
 

    COMPONENT D_FF_W_ENABLE_CLEAR PORT(
        D, E, ClearN, Clk: IN STD_LOGIC;
        Q: BUFFER STD_LOGIC);
    END COMPONENT;

    COMPONENT NOT_1 PORT(
        In0: IN STD_LOGIC;
        Out0: OUT STD_LOGIC);
    END COMPONENT;
 

BEGIN

    Reg4: FOR k IN size DOWNTO 0 GENERATE
        FlipFlop: D_FF_W_ENABLE_CLEAR PORT MAP(DMar(k), Esig, ClearNMar, clkMar, QMar(k));
    END GENERATE Reg4;

    U1: NOT_1 PORT MAP(LmN, Esig);

END Structural_REG_4_MAR_SAP_1;

Here is the D-flip flop code with a diagram to go with it:

Image below

Diagram

Sucessful D-flip flopenter image description here

I have created a Simulation of a 4 bit register in quartus. Each of the four D flip flops test fine by themselves, but when I test 4 of them connected together into a register, I get the "Error (suppressible): (vsim-3601) Iteration limit". If I assert the clear signal first (clearNMar, active low), I do not get the error and everything works fine...but I really should not HAVE to clear the register before using it. It should be "ok" for it to be undefined until the input signals are latched in. Below is the code...I will provide every component that I have used and its waveform building up to the register within reason. I am only allowed to post 8 links so I will not include the waveforms for the basic NOT, AND, NAND and OR gates. They definitely work though:

First, here is my 2 input AND gate:

--2 Input And Gate
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY AND_2 IS PORT(
    In0, In1: IN STD_LOGIC;
    Out0: OUT STD_LOGIC);
END AND_2;

ARCHITECTURE Dataflow_AND_2 of AND_2 IS
BEGIN
    Out0<=In0 AND In1;
END Dataflow_AND_2;

Next is the code for my 2 input NAND gate:

--dataflow model of a 2 input nand gate

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_2 IS PORT(
    In0, In1: IN STD_LOGIC;
    Out0: OUT STD_LOGIC);

END NAND_2;


ARCHITECTURE Dataflow OF NAND_2 IS
BEGIN
    Out0<= In0 NAND In1;
END Dataflow;

Next is my 3 Input NAND gate code:

--dataflow model of a 3 input nand gate

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_3 IS PORT(
    In0, In1, In2: IN STD_LOGIC;
    Out0: OUT STD_LOGIC);

END NAND_3;


ARCHITECTURE Dataflow OF NAND_3 IS
BEGIN
    Out0<= (NOT(In0 NAND In1)) NAND In2;
END Dataflow;

Next is the code for my NOT gate:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY NOT_1 IS PORT(
    In0: IN STD_LOGIC;
    Out0: OUT STD_LOGIC);
END NOT_1;

ARCHITECTURE Dataflow_NOT_1 OF NOT_1 IS
BEGIN
    Out0<= NOT In0;
END Dataflow_NOT_1;

Next is the code for my 3 input OR gate:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY OR_3 IS PORT(
    In0, In1, In2: IN STD_LOGIC;
    Out0: OUT STD_LOGIC);
END OR_3;

ARCHITECTURE Dataflow_OR_3 OF OR_3 IS
BEGIN
    Out0<= In0 OR In1 OR In2;
END Dataflow_OR_3;

Next is my multiplexer. A diagram, the code, and the simulation is shown below. I apologize that I was not able to figure out how to get the signals (N1, N2...etc) onto the simulation:

enter image description here

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX_2_1 IS PORT( 
    D0, D1, S: IN STD_LOGIC;
    Y: OUT STD_LOGIC);
END MUX_2_1;

ARCHITECTURE Structural_MUX_2_1 OF MUX_2_1 IS
    SIGNAL N1, N2, N3, N4: STD_LOGIC;

    COMPONENT NOT_1 PORT(
        In0: IN STD_LOGIC;
        Out0: OUT STD_LOGIC);
    END COMPONENT;

    COMPONENT AND_2 PORT(
        In0, In1: IN STD_LOGIC;
        Out0: OUT STD_LOGIC);
    END COMPONENT;

    COMPONENT OR_3 PORT(
        In0, In1, In2: IN STD_LOGIC;
        Out0: OUT STD_LOGIC);
    END COMPONENT;

BEGIN
    U1: NOT_1 PORT MAP(S, N1);
    U2: AND_2 PORT MAP(D0, N1, N2);
    U3: AND_2 PORT MAP(S, D1, N3);
    U4: AND_2 PORT MAP(D1, D0, N4);
    U5: OR_3 PORT MAP(N2, N3, N4, Y);

END Structural_MUX_2_1;

MUX

Here is the Diagram, Code and simulation of the D-flip flop which all works fine i think:

D-FlipFlop Diagram

DFlipSim

Finally, Here is the diagram, code and simulation of my register. I included the error simulation in which clearN(N means active low) is not asserted until a few clock cycles in, and the non-error simulation, when the clear is asserted at time "zero"

enter image description here

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY REG_4_MAR_SAP_1 IS 

    GENERIC(
    size: INTEGER:=3);

    --LmN is the load signal.  It is active low so there is a NOT gate 
leading into the E (enable) port of the D flip flop
    --clkMar is the clock for the register
    --clearNMar is the clear for the register which connects to the clear of the D flip flops...all active low.
    --DMar is the register input bus
    --QMar is the register output bus

    PORT(
    LmN, ClkMar, clearNMar: IN STD_LOGIC;
    DMar: IN STD_LOGIC_VECTOR(size DOWNTO 0);
    QMar: OUT STD_LOGIC_VECTOR(size DOWNTO 0));

END REG_4_MAR_SAP_1;

ARCHITECTURE Structural_REG_4_MAR_SAP_1 OF REG_4_MAR_SAP_1 IS

    Signal Esig: STD_LOGIC;


    COMPONENT D_FF_W_ENABLE_CLEAR PORT(
        D, E, ClearN, Clk: IN STD_LOGIC;
        Q: BUFFER STD_LOGIC);
    END COMPONENT;

    COMPONENT NOT_1 PORT(
        In0: IN STD_LOGIC;
        Out0: OUT STD_LOGIC);
    END COMPONENT;


BEGIN

    Reg4: FOR k IN size DOWNTO 0 GENERATE
        FlipFlop: D_FF_W_ENABLE_CLEAR PORT MAP(DMar(k), Esig, ClearNMar, clkMar, QMar(k));
    END GENERATE Reg4;

    U1: NOT_1 PORT MAP(LmN, Esig);

END Structural_REG_4_MAR_SAP_1;

Here is the Error condition when clearNMar is first asserted at 3us: enter image description here

Here is the successful condition when clearNMar is asserted at time= 0us: enter image description here

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