Timeline for When is proper to use <= or = assigments in Verilog
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Sep 23, 2018 at 23:21 | vote | accept | Alexis Hernandez | ||
| Sep 23, 2018 at 23:16 | comment | added | Brian Carlton | Welcome to Stack Exchange. You might try to get a minimal working example that shows your problem. That makes it easier to see your problem or others help you. | |
| S Sep 22, 2018 at 4:44 | history | suggested | dave_59 | CC BY-SA 4.0 |
fixed title
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| Sep 22, 2018 at 4:07 | review | Suggested edits | |||
| S Sep 22, 2018 at 4:44 | |||||
| Sep 22, 2018 at 4:00 | answer | added | dave_59 | timeline score: 2 | |
| Sep 22, 2018 at 3:21 | answer | added | D.A.S. | timeline score: -2 | |
| Sep 22, 2018 at 2:44 | history | asked | Alexis Hernandez | CC BY-SA 4.0 |