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I2C analog filter may provide wrong value, locking BUSY flag and preventing master mode entry

The I2C analog filters embedded in the I2C I/Os may be tied to low level, whereas SCL and SDA lines are kept at high level. This can occur after an MCU power-on reset, or during ESD stress. Consequently, the I2C BUSY flag is set, and the I2C cannot enter master mode (START condition cannot be sent). The I2C BUSY flag cannot be cleared by the SWRST control bit, nor by a peripheral or a system reset. BUSY bit is cleared under reset, but it is set high again as soon as the reset is released, because the analog filter output is still at low level. This issue occurs randomly. Note

Note: Under the same conditions, the I2C analog filters may also provide a high level, whereas SCL and SDA lines are kept to low level. This should not create issues as the filters output will be correct after next SCL and SDA transition. Workaround

Workaround The SCL and SDA analog filter output is updated after a transition occurs on the SCL and SDA line respectively. The SCL and SDA transition can be forced by software configuring the I2C I/Os in output mode. Then, once the analog filters are unlocked and output the SCL and SDA lines level, the BUSY flag can be reset with a software reset, and the I2C can enter master mode. Therefore, the following sequence must be applied:

  1. Disable the I2C peripheral by clearing the PE bit in I2Cx_CR1 register.
  2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
  3. Check SCL and SDA High level in GPIOx_IDR.
  4. Configure the SDA I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).
  5. Check SDA Low level in GPIOx_IDR.
  6. Configure the SCL I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).
  7. Check SCL Low level in GPIOx_IDR.
  8. Configure the SCL I/O as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
  9. Check SCL High level in GPIOx_IDR.
  10. Configure the SDA I/O as General Purpose Output Open-Drain , High level (Write 1 to GPIOx_ODR).
  11. Check SDA High level in GPIOx_IDR.
  12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.
  13. Set SWRST bit in I2Cx_CR1 register.
  14. Clear SWRST bit in I2Cx_CR1 register.
  15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register.

1. Disable the I2C peripheral by clearing the PE bit in I2Cx_CR1 register.

2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).

3. Check SCL and SDA High level in GPIOx_IDR.

4. Configure the SDA I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).

5. Check SDA Low level in GPIOx_IDR.

6. Configure the SCL I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).

7. Check SCL Low level in GPIOx_IDR.

8. Configure the SCL I/O as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).

9. Check SCL High level in GPIOx_IDR.

10. Configure the SDA I/O as General Purpose Output Open-Drain , High level (Write 1 to GPIOx_ODR).

11. Check SDA High level in GPIOx_IDR.

12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.

13. Set SWRST bit in I2Cx_CR1 register.

14. Clear SWRST bit in I2Cx_CR1 register.

15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register.

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The I2C analog filters embedded in the I2C I/Os may be tied to low level, whereas SCL and SDA lines are kept at high level. This can occur after an MCU power-on reset, or during ESD stress. Consequently, the I2C BUSY flag is set, and the I2C cannot enter master mode (START condition cannot be sent). The I2C BUSY flag cannot be cleared by the SWRST control bit, nor by a peripheral or a system reset. BUSY bit is cleared under reset, but it is set high again as soon as the reset is released, because the analog filter output is still at low level. This issue occurs randomly. Note: Under the same conditions, the I2C analog filters may also provide a high level, whereas SCL and SDA lines are kept to low level. This should not create issues as the filters output will be correct after next SCL and SDA transition. Workaround The SCL and SDA analog filter output is updated after a transition occurs on the SCL and SDA line respectively. The SCL and SDA transition can be forced by software configuring the I2C I/Os in output mode. Then, once the analog filters are unlocked and output the SCL and SDA lines level, the BUSY flag can be reset with a software reset, and the I2C can enter master mode. Therefore, the following sequence must be applied:

  1. Disable the I2C peripheral by clearing the PE bit in I2Cx_CR1 register.
  2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
  3. Check SCL and SDA High level in GPIOx_IDR.
  4. Configure the SDA I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).
  5. Check SDA Low level in GPIOx_IDR.
  6. Configure the SCL I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).
  7. Check SCL Low level in GPIOx_IDR.
  8. Configure the SCL I/O as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
  9. Check SCL High level in GPIOx_IDR.
  10. Configure the SDA I/O as General Purpose Output Open-Drain , High level (Write 1 to GPIOx_ODR).
  11. Check SDA High level in GPIOx_IDR.
  12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.
  13. Set SWRST bit in I2Cx_CR1 register.
  14. Clear SWRST bit in I2Cx_CR1 register.
  15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register.

more

I2C analog filter may provide wrong value, locking BUSY flag and preventing master mode entry

The I2C analog filters embedded in the I2C I/Os may be tied to low level, whereas SCL and SDA lines are kept at high level. This can occur after an MCU power-on reset, or during ESD stress. Consequently, the I2C BUSY flag is set, and the I2C cannot enter master mode (START condition cannot be sent). The I2C BUSY flag cannot be cleared by the SWRST control bit, nor by a peripheral or a system reset. BUSY bit is cleared under reset, but it is set high again as soon as the reset is released, because the analog filter output is still at low level. This issue occurs randomly.

Note: Under the same conditions, the I2C analog filters may also provide a high level, whereas SCL and SDA lines are kept to low level. This should not create issues as the filters output will be correct after next SCL and SDA transition.

Workaround The SCL and SDA analog filter output is updated after a transition occurs on the SCL and SDA line respectively. The SCL and SDA transition can be forced by software configuring the I2C I/Os in output mode. Then, once the analog filters are unlocked and output the SCL and SDA lines level, the BUSY flag can be reset with a software reset, and the I2C can enter master mode. Therefore, the following sequence must be applied:

1. Disable the I2C peripheral by clearing the PE bit in I2Cx_CR1 register.

2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).

3. Check SCL and SDA High level in GPIOx_IDR.

4. Configure the SDA I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).

5. Check SDA Low level in GPIOx_IDR.

6. Configure the SCL I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).

7. Check SCL Low level in GPIOx_IDR.

8. Configure the SCL I/O as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).

9. Check SCL High level in GPIOx_IDR.

10. Configure the SDA I/O as General Purpose Output Open-Drain , High level (Write 1 to GPIOx_ODR).

11. Check SDA High level in GPIOx_IDR.

12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.

13. Set SWRST bit in I2Cx_CR1 register.

14. Clear SWRST bit in I2Cx_CR1 register.

15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register.

more

Source Link
Hamed
Hamed
  • 117
  • 1
  • 6

The I2C analog filters embedded in the I2C I/Os may be tied to low level, whereas SCL and SDA lines are kept at high level. This can occur after an MCU power-on reset, or during ESD stress. Consequently, the I2C BUSY flag is set, and the I2C cannot enter master mode (START condition cannot be sent). The I2C BUSY flag cannot be cleared by the SWRST control bit, nor by a peripheral or a system reset. BUSY bit is cleared under reset, but it is set high again as soon as the reset is released, because the analog filter output is still at low level. This issue occurs randomly. Note: Under the same conditions, the I2C analog filters may also provide a high level, whereas SCL and SDA lines are kept to low level. This should not create issues as the filters output will be correct after next SCL and SDA transition. Workaround The SCL and SDA analog filter output is updated after a transition occurs on the SCL and SDA line respectively. The SCL and SDA transition can be forced by software configuring the I2C I/Os in output mode. Then, once the analog filters are unlocked and output the SCL and SDA lines level, the BUSY flag can be reset with a software reset, and the I2C can enter master mode. Therefore, the following sequence must be applied:

  1. Disable the I2C peripheral by clearing the PE bit in I2Cx_CR1 register.
  2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
  3. Check SCL and SDA High level in GPIOx_IDR.
  4. Configure the SDA I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).
  5. Check SDA Low level in GPIOx_IDR.
  6. Configure the SCL I/O as General Purpose Output Open-Drain, Low level (Write 0 to GPIOx_ODR).
  7. Check SCL Low level in GPIOx_IDR.
  8. Configure the SCL I/O as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
  9. Check SCL High level in GPIOx_IDR.
  10. Configure the SDA I/O as General Purpose Output Open-Drain , High level (Write 1 to GPIOx_ODR).
  11. Check SDA High level in GPIOx_IDR.
  12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.
  13. Set SWRST bit in I2Cx_CR1 register.
  14. Clear SWRST bit in I2Cx_CR1 register.
  15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register.

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