Timeline for DP83848 + STM32 & Failed EMC (massive spikes of 25MHz crystal harmonics)
Current License: CC BY-SA 4.0
15 events
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| Nov 15, 2018 at 8:43 | history | edited | wildfireheart | CC BY-SA 4.0 |
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| Nov 15, 2018 at 8:40 | comment | added | wildfireheart | @Dan Mills Yes, the USB layout is wrong, it should be differential pair as you say. Nonetheless, we use it only for serial port emulation, it works and we haven't had a problem with it in terms of EMI in this design. We will do it properly in next designs of course. | |
| Nov 15, 2018 at 8:37 | history | edited | wildfireheart | CC BY-SA 4.0 |
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| Nov 15, 2018 at 7:57 | vote | accept | wildfireheart | ||
| Nov 13, 2018 at 13:03 | comment | added | Dan Mills | Not directly related but either the ethernet controlled impedance nets or the USB controlled impedance nets look wrong to me, they should be about the same impedance (90 Vs 100R) but have very different geometry on your board. Also the USB nets should be routed as a differential pair which means vias close together (Look under the crystal X-16M), but I suspect the USB net geometry is rather higher impedance then it should be overall. You might well have a conducted emissions issue with the USB interface as well as your radiated problems. | |
| Nov 13, 2018 at 0:00 | history | tweeted | twitter.com/StackElectronix/status/1062132950890885120 | ||
| Nov 9, 2018 at 12:28 | answer | added | Dan Mills | timeline score: 7 | |
| Nov 9, 2018 at 5:52 | comment | added | wildfireheart | @ajb Yeah, the MII lines don't look too good now that I look at it. Thanks for the tip with RMII, we will try it with current board together with some mentioned hacks and then probably redo the PCB, so there are no gaps in planes below PHY<->MCU wires and so we have more capacitance and filtering on power pins. | |
| Nov 9, 2018 at 3:36 | answer | added | analogsystemsrf | timeline score: 5 | |
| Nov 9, 2018 at 3:29 | comment | added | analogsystemsrf | What are those long traces running along top of the board? | |
| Nov 8, 2018 at 20:52 | comment | added | ajb | You have substantial breaks in both of your reference planes under the MII signals. That's no good. You can probably do a bit better just by rearranging your traces, but you may get better results if you can switch to RMII, it's twice the clock freq but half the signals. You probably want additional capacitance near the PHY (and the MCU) beyond just the decouplers, hard to tell without evaluating your power network. | |
| Nov 8, 2018 at 20:36 | history | edited | wildfireheart | CC BY-SA 4.0 |
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| Nov 8, 2018 at 18:39 | comment | added | wildfireheart | @Peter Karlsen There is 100nF capacitor on every supply pin from the bottom side of the PCB. | |
| Nov 8, 2018 at 16:21 | comment | added | Peter Karlsen | Looks like you have no supply decoupling a all on the PHY chip. You shouldn't be using your GND and PWR plane layers for routing. | |
| Nov 8, 2018 at 16:02 | history | asked | wildfireheart | CC BY-SA 4.0 |