Timeline for Why does this file give syntax error in verilog?
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
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| Mar 30, 2019 at 23:09 | vote | accept | CommunityBot | ||
| Mar 30, 2019 at 23:09 | history | edited | user170589 | CC BY-SA 4.0 |
deleted 158 characters in body
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| Mar 30, 2019 at 23:01 | history | edited | user170589 | CC BY-SA 4.0 |
added 129 characters in body
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| Mar 30, 2019 at 22:53 | answer | added | Dave Tweed | timeline score: 0 | |
| Mar 30, 2019 at 21:58 | comment | added | user170589 | @ThePhoton Yes because it is the output of the schematic | |
| Mar 30, 2019 at 21:57 | history | edited | user170589 | CC BY-SA 4.0 |
added 63 characters in body
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| Mar 30, 2019 at 21:56 | comment | added | user170589 | @ThePhoton yes one moment please , see edits | |
| Mar 30, 2019 at 21:56 | comment | added | The Photon | One thing, you didn't name your last or gate like you did the other gates. | |
| Mar 30, 2019 at 21:54 | comment | added | The Photon | Please share the complete error messages. It will make it much easier to find the problem. | |
| Mar 30, 2019 at 21:27 | history | asked | user170589 | CC BY-SA 4.0 |