Notice there is NO SPEC for power supply rejection, despite the rather large Deterministic Jitter contribution. Given the high bandwidth, the CML gate is also vulnerable to trash induced on the input and output traces; either shield the traces, or keep high-slew-rate signals (logic of MCUs, switching supplies) well away from the CML traces.

View those 50 picosecond edges as just another version of 20GigaHertz sampler, with all the trash energy down-converted into and on top of your datastream, causing bit errors and edge jitter that degrades the bathtub dataeye.

Notice there is NO SPEC for power supply rejection, despite the rather large Deterministic Jitter contribution. Given the high bandwidth, the CML gate is also vulnerable to trash induced on the input and output traces; either shield the traces, or keep high-slew-rate signals (logic of MCUs, switching supplies) well away from the CML traces.

View those 50 picosecond edges as just another version of 20GigaHertz sampler, with all the trash energy down-converted into and on top of your datastream, causing bit errors and edge jitter that degrades the bathtub dataeye.

Example: suppose there is 1pF coupling between a normal (2.5 volt/ 0.25nanoscond) MCU signal; this is 10 volts per nanosecond, or 10^10 volts per second. How much current couples thru the 1pF? I = C * dV/dT

I = 1pF * 10^10 volt/sec = 10^-12 Farad * 10^+10 volt/sec = 10^-2

I = 0.01 amps.

Now with 50 ohm termination, the dV is just Ohma Law: V = I * R.

V levelshift is 0.01 * 50 = 0.5 volts. In other words, nearly fast edges will inject a dangerous (very large charge upsets, causing lots of Deterministic Jitter) amount of current.