Timeline for STM32 USART synchronous mode receive does not work
Current License: CC BY-SA 4.0
12 events
| when toggle format | what | by | license | comment | |
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| Apr 17, 2019 at 0:10 | comment | added | Fr4nky | You are correct, I already added the solution to my answer. | |
| Apr 16, 2019 at 0:00 | comment | added | Chris Stratton | As a guess, you may get the overrun error by ignoring the read side when doing what you think of as writes. The hardware doesn't have any real way to know that you don't care about what is being clocked in on MISO at that point. | |
| Apr 15, 2019 at 23:54 | vote | accept | Fr4nky | ||
| Apr 15, 2019 at 23:54 | history | edited | Fr4nky | CC BY-SA 4.0 |
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| Apr 15, 2019 at 23:53 | comment | added | Fr4nky | It was indeed the overrun error bit, disabling the overrun detection solved the problem. I ignored it until now as I thought it was only a status bit that has no influence on the functionality but the reference manual explains it in a note: "When this bit is set, the RDR register content is not lost but the shift register is overwritten." No new RDR data also means the RXNE flag doesn't get set. | |
| Apr 15, 2019 at 19:35 | comment | added | Chris Stratton | You're probably letting it get into a bad state, which resetting it is undoing. Try reading out all of the status/flag/error registers before and after the reset. | |
| Apr 15, 2019 at 19:31 | history | edited | Fr4nky | CC BY-SA 4.0 |
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| Apr 15, 2019 at 19:25 | history | undeleted | Fr4nky | ||
| Apr 15, 2019 at 19:25 | history | edited | Fr4nky | CC BY-SA 4.0 |
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| Apr 15, 2019 at 19:19 | history | edited | Fr4nky | CC BY-SA 4.0 |
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| Apr 15, 2019 at 18:54 | history | deleted | Fr4nky | via Vote | |
| Apr 15, 2019 at 18:50 | history | answered | Fr4nky | CC BY-SA 4.0 |