I didn't read your entire wall of text, but I don't think the answers to your questions depend on much of what you wrote.
I have the datasheets of both ICs. Where is it written, implied or can be calculated/extracted the input/output impedance of the pins?
Different vendors have different conventions for how they report it. One might report an output impedance. One might report an \$|S_{22}|\$ limit. One might report a typical \$S_{22}(f)\$ curve. You'll have to read each individual datasheet and see how they spec their chip.
For some kinds of ICs, input and output impedances aren't specified at all.
Is the output impedance the same as input impedance for I/O pins?
Not necessarily. For a digital buffer, you'd expect input impedance to be very high and output impedance to be very low, for example.
Does the specification of the protocol (in this case LVCMOS33) specifies the I/O impedance?
For CMOS, yes, you can expect a "very low" output impedance, maybe a few ohms. And input impedance will be dominated by capacitance, which will very often be specified.
How a designer is supposed to know that impedances match between those 2 ICs so a controlled line is all that is required?
For CMOS designs, generally you don't match impedances, you just keep the lines short enough that it doesn't matter. A few ohms series resistance on drivers may be used to reduce ringing, but still an actual matched termination is not expected.
One thing I did pick out of your text,
For 0.8 ns PCB Toolkit reports a max trace length of 1.25 inches.
One option is to use a series resistor at the source to increase the rise and fall times. If you increase the edge time to a more reasonable 2 ns (for a 10 ns clock period), you will get a maximum unmatched trace length that's much easier to work with.