Timeline for How do you know if impedance is the same for 2 ICs?
Current License: CC BY-SA 4.0
13 events
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| Apr 26, 2019 at 18:41 | comment | added | The Photon | @Manos, I'd rather put the resistor location and stuff it with 0 ohms if I decide I don't need it than not put the resistor location and have to re-spin the board if I decide I do need it. You will probably want to use a 4- or 8-resistor array to save space. | |
| Apr 26, 2019 at 18:25 | vote | accept | Manos | ||
| Apr 26, 2019 at 18:22 | comment | added | Manos | @ThePhoton Thank you very much for remembering to check it out! Today I found out that configuring the output of the FPGA as LVCMOS33, 4 mA results in 50Ω impedance according to the generated IBIS. FT is also configurable as 50Ω so I am in favor of omitting the R's, am I correct? Simulation seems fine, very low undershoot/overshoot (<=40mV) | |
| Apr 26, 2019 at 16:55 | comment | added | The Photon | @Manos, my project used 33-ohm series termination on the FTDI side, no termination on the FPGA side. Trace length is ~1 inch. No known issues with this interface with dozens of boards deployed in the field. | |
| Apr 26, 2019 at 7:22 | comment | added | joribama | @Manos - I understand your frustration in trying to fill the gap between theory and practice in the field of signal integrity. I'm not familiar with the parts you're using nor with which particular pin is connected to. Anyways, if you're connecting regular logic signals you're better off simply using series termination at the source so that the external resistor plus the internal output impedance of the driver equals the characteristic impedance of the trace. If they are bidirectional and at any given time each side is either an input or output, I would have series resistors on both ends. | |
| Apr 26, 2019 at 2:20 | comment | added | The Photon | @Manos, I will double-check it tomorrow. | |
| Apr 26, 2019 at 2:18 | comment | added | Manos | So you mean that 2 inch traces is safe distance and no R's were used? I am asking because simulation in Alitum with 1.3 inch 50Ω traces was showing significant distortion. | |
| Apr 26, 2019 at 2:12 | comment | added | The Photon | I've got a FT601 based design on my bench right now, but it isn't my design so all I can tell you is that the parallel bus is not what caused problems. Probably we have the FT601 within 2 inches of the FPGA it talks to, though (can check this tomorrow). | |
| Apr 26, 2019 at 1:58 | comment | added | Manos | Of course, FT601 and MachXO2. Again, thanks for your response. | |
| Apr 26, 2019 at 1:47 | comment | added | The Photon | @Manos, care to share the part number (or provide a link to the datasheet in your post) for the parts you're considering? | |
| Apr 26, 2019 at 1:29 | comment | added | Manos | Thanks a lot for your answer, although it does not clear things entirely it makes me feel more confident about my design. A last question I would like to elaborate if you could (which probably did not read on my text) is that many of these lines are are bidirectional. Generally, I understand that you place a series resistor at the output. In case of a bidirectional, since they both function as output and input where do you place the R? Or you place one in both sides? An answer in my previous question suggested one R and in short lengths below 2-3 inches doesn't really matter where is placed. | |
| Apr 25, 2019 at 21:47 | history | edited | The Photon | CC BY-SA 4.0 |
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| Apr 25, 2019 at 21:42 | history | answered | The Photon | CC BY-SA 4.0 |