Timeline for Are nested modules allowed in Verilog?
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| S Jun 7, 2019 at 10:51 | history | suggested | vineeshvs | CC BY-SA 4.0 |
added better formatting
|
| Jun 7, 2019 at 5:59 | review | Suggested edits | |||
| S Jun 7, 2019 at 10:51 | |||||
| Apr 26, 2019 at 15:16 | vote | accept | vineeshvs | ||
| Apr 26, 2019 at 15:15 | review | First posts | |||
| Apr 26, 2019 at 15:25 | |||||
| Apr 26, 2019 at 15:10 | history | answered | kbkr | CC BY-SA 4.0 |