Timeline for Inconsistent SPI communication between STM32F4 (Slave) and Raspberry Pi (Master)
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 10, 2020 at 9:20 | answer | added | user3185951 | timeline score: 0 | |
| Apr 30, 2019 at 16:07 | answer | added | Jeff McBride | timeline score: 2 | |
| Apr 30, 2019 at 14:37 | comment | added | Andy aka | Slave responses are clocked out by the master and are hence delayed relative to the clock signal generated by the master. The delay is twofold and this is because the slave response is lagging due to interconnection length and the slave transmission lags by one more transmission length back to the master. This can sometimes mean problems over several cm at high clock rates. | |
| Apr 30, 2019 at 13:34 | comment | added | Amudsen | From the Slave? I mean the slave accepts whatever clock is coming from the Master, no? I tried a range of clocks from 100kHz to few MHz the behaviour seems to be similar (just less/more frequent resets). Physically maybe few cm's but there are no jumper cables, all signals go via a custom PCB. The clock and data signals looked quite clear on oscilloscope last time I checked. | |
| Apr 30, 2019 at 11:52 | comment | added | Andy aka | What clock speed are you clocking the data from the slave and how far physically is the slave from the clocking master? | |
| Apr 30, 2019 at 11:15 | review | First posts | |||
| Apr 30, 2019 at 11:21 | |||||
| Apr 30, 2019 at 11:12 | history | asked | Amudsen | CC BY-SA 4.0 |