2 added 3 characters in body
source | link

Despite low-pass hardware filters on ADC inputs I am having a lot of erratic readings. There are 8 single-ended channels in DMA sequence and it is configured for cyclic sampling. Sampling time is set to maximum (601 cycles). The inputs connected to feedback resistors in actuators. Unfortunately, the power wires and feedback wires are in the same cable, without any shielding between them, so some noise is expected.

The results, however, are worse than expected - out of 4M samplings about 200K have more than 20 difference between subsequent valuesconsecutive readings, with maximum difference exceeding 2000 (on 4096 ADC range).

Now, my understanding is that "memory data size" in DMA configuration means it won't be changing one byte of the 16-bit conversion result while MCU is reading the other. Although it might simply be used for data re-packaging.

Just in case, I've replaced one target memory buffer with two and used half-transfer-complete/transfer-complete interrupts to make sure MCU is reading from one buffer while DMA is filling another. Did not make any difference.

The questions:

  • does "memory data size" safeguard from concurrent multi-byte memory access in any way?

  • if not, what else can I do to reduce noise? For example one trick on Atmel chips was to read and discard first ADC value, then read same channel again. I am not sure I can do this with cyclic configuration.

Note, that I am not asking for SW filtering methods. I have those prepared and tested many times before, and will use them in the final implementation anyway. What I am hoping for is some advice on reducing amount of spikes in the raw ADC output to begin with.

Despite low-pass hardware filters on ADC inputs I am having a lot of erratic readings. There are 8 single-ended channels in DMA sequence and it is configured for cyclic sampling. Sampling time is set to maximum (601 cycles). The inputs connected to feedback resistors in actuators. Unfortunately, the power wires and feedback wires are in the same cable, without any shielding between them, so some noise is expected.

The results, however, are worse than expected - out of 4M samplings about 200K have more than 20 difference between subsequent values, with maximum difference exceeding 2000 (on 4096 ADC range).

Now, my understanding is that "memory data size" in DMA configuration means it won't be changing one byte of the 16-bit conversion result while MCU is reading the other. Although it might simply be used for data re-packaging.

Just in case, I've replaced one target memory buffer with two and used half-transfer-complete/transfer-complete interrupts to make sure MCU is reading from one buffer while DMA is filling another. Did not make any difference.

The questions:

  • does "memory data size" safeguard from concurrent multi-byte memory access in any way?

  • if not, what else can I do to reduce noise? For example one trick on Atmel chips was to read and discard first ADC value, then read same channel again. I am not sure I can do this with cyclic configuration.

Note, that I am not asking for SW filtering methods. I have those prepared and tested many times before, and will use them in the final implementation anyway. What I am hoping for is some advice on reducing amount of spikes in the raw ADC output to begin with.

Despite low-pass hardware filters on ADC inputs I am having a lot of erratic readings. There are 8 single-ended channels in DMA sequence and it is configured for cyclic sampling. Sampling time is set to maximum (601 cycles). The inputs connected to feedback resistors in actuators. Unfortunately, the power wires and feedback wires are in the same cable, without any shielding between them, so some noise is expected.

The results, however, are worse than expected - out of 4M samplings about 200K have more than 20 difference between consecutive readings, with maximum difference exceeding 2000 (on 4096 ADC range).

Now, my understanding is that "memory data size" in DMA configuration means it won't be changing one byte of the 16-bit conversion result while MCU is reading the other. Although it might simply be used for data re-packaging.

Just in case, I've replaced one target memory buffer with two and used half-transfer-complete/transfer-complete interrupts to make sure MCU is reading from one buffer while DMA is filling another. Did not make any difference.

The questions:

  • does "memory data size" safeguard from concurrent multi-byte memory access in any way?

  • if not, what else can I do to reduce noise? For example one trick on Atmel chips was to read and discard first ADC value, then read same channel again. I am not sure I can do this with cyclic configuration.

Note, that I am not asking for SW filtering methods. I have those prepared and tested many times before, and will use them in the final implementation anyway. What I am hoping for is some advice on reducing amount of spikes in the raw ADC output to begin with.

1
source | link

MultiByte data integrity with DMA on STM32F3

Despite low-pass hardware filters on ADC inputs I am having a lot of erratic readings. There are 8 single-ended channels in DMA sequence and it is configured for cyclic sampling. Sampling time is set to maximum (601 cycles). The inputs connected to feedback resistors in actuators. Unfortunately, the power wires and feedback wires are in the same cable, without any shielding between them, so some noise is expected.

The results, however, are worse than expected - out of 4M samplings about 200K have more than 20 difference between subsequent values, with maximum difference exceeding 2000 (on 4096 ADC range).

Now, my understanding is that "memory data size" in DMA configuration means it won't be changing one byte of the 16-bit conversion result while MCU is reading the other. Although it might simply be used for data re-packaging.

Just in case, I've replaced one target memory buffer with two and used half-transfer-complete/transfer-complete interrupts to make sure MCU is reading from one buffer while DMA is filling another. Did not make any difference.

The questions:

  • does "memory data size" safeguard from concurrent multi-byte memory access in any way?

  • if not, what else can I do to reduce noise? For example one trick on Atmel chips was to read and discard first ADC value, then read same channel again. I am not sure I can do this with cyclic configuration.

Note, that I am not asking for SW filtering methods. I have those prepared and tested many times before, and will use them in the final implementation anyway. What I am hoping for is some advice on reducing amount of spikes in the raw ADC output to begin with.