To put it simple: The typical setup is

in case your µC has distinct –RD and –WR signals

• wire the address decoder output to the –CS input of the RAM chip.
• wire the –WR output of the µC to the –WE input of the RAM chip.
• wire the –RD output of the µC to the –OE input of the RAM chip.

in case your µC has an R/-W output

• wire the address decoder output to the –CS input of the RAM chip.
• wire the R/-W output of the µC to the –WE input of the RAM chip.
• wire the inverted R/–W output of the µC and the –CS input on the RAM chip though an OR gate to the –OE input of the RAM chip.

No further magic needed. If you happen to need any delays for more exotic chips —none come to my mind prominently—, you don't do that with an NE555 or similar but with the propagation delay of inverters, which is in the 5ns range for the 74xx gate series and in the 40ns range for the 40xx gate series at 5V.

To put it simple: The typical setup is

in case your µC has distinct –RD and –WR outputs (e.g. Z80)

• wire the address decoder output to the –CS input of the RAM chip.
• wire the –WR output of the µC to the –WE input of the RAM chip.
• wire the –RD output of the µC to the –OE input of the RAM chip.

in case your µC has an R/-W output (e.g. 6502)

• wire the address decoder output to the –CS input of the RAM chip.
• wire the R/-W output of the µC to the –WE input of the RAM chip.
• wire the inverted R/–W output of the µC and the –CS input on the RAM chip though an OR gate to the –OE input of the RAM chip.

No further magic needed. If you happen to need any delays for more exotic chips —none come to my mind prominently—, you don't do that with an NE555 or similar but with the propagation delay of inverters, which is in the 5ns range for the 74xx gate series and in the 40ns range for the 40xx gate series at 5V.