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Deleted my comment about "no internal clock" because it was Just Plain Wrong.
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Mr. Snrub
Mr. Snrub
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Here is another answer on StackExchange which explains pin assignment for Lattice devices: https://electronics.stackexchange.com/a/232013/213609

Regarding the clock you are correct; the FPGA will just sit there until it gets a clock input; it does not have any internal clock capability. You'll need a function generator or some way to create a square-wave signal to use as your clock.

As a starting point, I'd suggest you just synthesize some super-primitive combinatorial logic like a NOT gate or even just fixed '0' and '1' values so you can prove to yourself that you're getting the pin assignments correct. Once that's working, then move on to the counter with its CLK and RST signals.

Here is another answer on StackExchange which explains pin assignment for Lattice devices: https://electronics.stackexchange.com/a/232013/213609

Regarding the clock you are correct; the FPGA will just sit there until it gets a clock input; it does not have any internal clock capability. You'll need a function generator or some way to create a square-wave signal to use as your clock.

As a starting point, I'd suggest you just synthesize some super-primitive combinatorial logic like a NOT gate or even just fixed '0' and '1' values so you can prove to yourself that you're getting the pin assignments correct. Once that's working, then move on to the counter with its CLK and RST signals.

Here is another answer on StackExchange which explains pin assignment for Lattice devices: https://electronics.stackexchange.com/a/232013/213609

As a starting point, I'd suggest you just synthesize some super-primitive combinatorial logic like a NOT gate or even just fixed '0' and '1' values so you can prove to yourself that you're getting the pin assignments correct. Once that's working, then move on to the counter with its CLK and RST signals.

Source Link
Mr. Snrub
Mr. Snrub
  • 2.6k
  • 9
  • 12

Here is another answer on StackExchange which explains pin assignment for Lattice devices: https://electronics.stackexchange.com/a/232013/213609

Regarding the clock you are correct; the FPGA will just sit there until it gets a clock input; it does not have any internal clock capability. You'll need a function generator or some way to create a square-wave signal to use as your clock.

As a starting point, I'd suggest you just synthesize some super-primitive combinatorial logic like a NOT gate or even just fixed '0' and '1' values so you can prove to yourself that you're getting the pin assignments correct. Once that's working, then move on to the counter with its CLK and RST signals.