I am writing a really simple program on Verilog for my FPGA to have an LED blink once a button is pushed. Here is the code I have written:

module hello_world(
   input ron,           //reset button (ron = reset/on) 
   input clk,           //clk, on board clk is 25 MHz
   output reg led1,     //led to blink
   output reg start);   //problematic signal
    
reg [22:0] led;
always @(posedge clk) begin 
    if(!ron) begin
        led <= 0;
        start <= 1;
    end

    if(start) begin
        if(ron)
            led <= led + 23'b00000000000000000000001;
        led1 <= led[22];
    end
end


endmodule

I know there are probably cleaner ways of doing this, but I'm just doing this way, and there is a really weird problem that is occurring. The 'start' register is being set to 1 before I even hit the 'ron' button (reset/on button) and I have no clue why. This problem is happening with any register that I assign 1 to in the if statement.

I tried simulating it in ModelSim, and it seems to run fine, but on the FPGA board (Polmaddie7) it assigns start to 1 before the button is hit.

I would appreciate any help on this please. If I have left any information out that would be helpful to understanding/answering this, please let me know.

I am writing a really simple program on Verilog for my FPGA to have an LED blink once a button is pushed. Here is the code I have written:

module hello_world(
   input ron,           //reset button (ron = reset/on) 
   input clk,           //clk, on board clk is 25 MHz
   output reg led1,     //led to blink
   output reg start);   //problematic signal
    
reg [22:0] led;
always @(posedge clk) begin 
    if(!ron) begin
        led <= 0;
        start <= 1;
    end

    if(start) begin
        led <= led + 23'b00000000000000000000001;
        led1 <= led[22];
    end
end


endmodule

I know there are probably cleaner ways of doing this, but I'm just doing this way, and there is a really weird problem that is occurring. The 'start' register is being set to 1 before I even hit the 'ron' button (reset/on button) and I have no clue why. This problem is happening with any register that I assign 1 to in the if statement.

I tried simulating it in ModelSim, and it seems to run fine, but on the FPGA board (Polmaddie7) it assigns start to 1 before the button is hit.

I would appreciate any help on this please. If I have left any information out that would be helpful to understanding/answering this, please let me know.

I am writing a really simple program on Verilog for my FPGA to have an LED blink once a button is pushed. Here is the code I have written:

module hello_world(
   input ron,           //reset button (ron = reset/on) 
   input clk,           //clk, on board clk is 25 MHz
   output reg led1,     //led to blink
   output reg start);   //problematic signal
    
reg [22:0] led;
always @(posedge clk) begin 
    if(!ron) begin
        led <= 0;
        start <= 1;
    end

    if(start) begin
        if(ron)
            led <= led + 23'b00000000000000000000001;
        led1 <= led[22];
    end
end


endmodule

I know there are probably cleaner ways of doing this, but I'm just doing this way, and there is a really weird problem that is occurring. The 'start' register is being set to 1 before I even hit the 'ron' button (reset/on button) and I have no clue why. I tried simulating it in ModelSim, and it seems to run fine, but on the FPGA board (Polmaddie7) it assigns start to 1 before the button is hit. I would appreciate any help on this please. If I have left any information out that would be helpful to understanding/answering this, please let me know.

I am writing a really simple program on Verilog for my FPGA to have an LED blink once a button is pushed. Here is the code I have written:

module hello_world(
   input ron,           //reset button (ron = reset/on) 
   input clk,           //clk, on board clk is 25 MHz
   output reg led1,     //led to blink
   output reg start);   //problematic signal
    
reg [22:0] led;
always @(posedge clk) begin 
    if(!ron) begin
        led <= 0;
        start <= 1;
    end

    if(start) begin
        if(ron)
            led <= led + 23'b00000000000000000000001;
        led1 <= led[22];
    end
end


endmodule

I know there are probably cleaner ways of doing this, but I'm just doing this way, and there is a really weird problem that is occurring. The 'start' register is being set to 1 before I even hit the 'ron' button (reset/on button) and I have no clue why. This problem is happening with any register that I assign 1 to in the if statement.

I tried simulating it in ModelSim, and it seems to run fine, but on the FPGA board (Polmaddie7) it assigns start to 1 before the button is hit. 

I would appreciate any help on this please. If I have left any information out that would be helpful to understanding/answering this, please let me know.