Timeline for Why are registers being turned on to 1 before reset/on button is hit on FPGA?
Current License: CC BY-SA 4.0
12 events
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| Sep 6, 2019 at 6:06 | comment | added | Mitu Raj | In Altera FPGAs, global reset happens at start up and it automatically resets to the values you either specified as initial values or the values given in the reset block. If both mismatch, synthesiser throws a warning as well :) | |
| Sep 5, 2019 at 21:56 | comment | added | Tom Carpenter | The synthesis tool may also be doing bubble pushing. If it infers that you want the register to reset to 1 (based on the code describing a synchronous reset), it can add inverters to the data in and data out of the storage register(s). That way the FPGA on configure can (if supported) simply set all registers to zero, and the inverter will take care of it appering as 1 to the rest of the circuit. | |
| Sep 5, 2019 at 20:54 | vote | accept | Lokwill | ||
| Sep 5, 2019 at 20:51 | comment | added | The Photon |
Just what I said in my answer: "In this case you need to code the reset behavior of start as going to 0, and use ron as an ordinary signal". You can either use an initial block, or an if(greset) begin ... end else begin ... end structure in your code to implement the reset behavior.
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| Sep 5, 2019 at 20:49 | comment | added | Lokwill |
So how would I have it not assert !ron? You mentioned using it as an ordinary signal, but I thought that's what I'm doing now.
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| Sep 5, 2019 at 20:49 | comment | added | The Photon |
However if you disable global reset, then what state start comes up in is unpredictable. It might always be 1, might always be 0, might sometimes be 1 and sometimes 0, etc. You're much better off using global reset and explicitly choosing which way your signals come up.
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| Sep 5, 2019 at 20:47 | comment | added | The Photon |
@Lokwill, if the FPGA has automatic global reset, it will automatically assert !ron at start-up (and in a way that the clock doesn't matter), regardless of what your code says. There might be a way to disable this, but how to do it would depend on exactly which FPGA you're using.
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| Sep 5, 2019 at 20:46 | comment | added | Lokwill |
Hmm, I'm still confused. I am relatively new to the FPGA world. I don't understand how led is 0 and start is 1 if my code says that this should only happen when !ron occurs.
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| Sep 5, 2019 at 20:42 | comment | added | The Photon | @Lokwill, that wasn't really what I should have said. I've corrected the answer post. | |
| Sep 5, 2019 at 20:42 | history | edited | The Photon | CC BY-SA 4.0 |
added 7 characters in body
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| Sep 5, 2019 at 20:38 | comment | added | Lokwill |
What do you mean by dedicated reset routing resources, when specifying the pin for the ron I just assigned it to a button? Can you elaborate on what you mean by using ron as an ordinary signal causing a transition?
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| Sep 5, 2019 at 20:34 | history | answered | The Photon | CC BY-SA 4.0 |