Consider a successive approximation ADC. Each step size successively halves the step size at the previous step, so teh first step (for the MSB) compares the input with Vref/2.

Then successive steps are smaller powers of 2, until ... 4095? No, 4096.

Now the ADC can output 4096 codes, from 0 to ... 4095.

Therefore it cannot accurately represent an input voltage exactly equal to Vref ... effectively rounding it down to the code immediately below, i.e. 4095.

Consider a successive approximation ADC. Each step size successively halves the step size at the previous step, so teh first step (for the MSB) compares the input with Vref/2.

Then successive steps are smaller powers of 2, until ... 4095? No, 4096.

Now the ADC can output 4096 codes, from 0 to ... 4095.

Every output code is effectively "rounded down" to the largest step below it (in an ideal model of an ADC), this is a consequence of the comparator step

Therefore it cannot accurately represent an input voltage exactly equal to Vref ... effectively rounding it down to the code immediately below, i.e. 4095.

In practice of course you have to deal with the errors in non-ideal ADCs, as descried in Andy's answer.