Timeline for Making a simple 4 bit adder into a 4 bit adder with carry in & out
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
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| Oct 23, 2019 at 9:09 | comment | added | scary_jeff |
If your inputs and outputs are signed numbers, you can give them type signed instead of std_logic_vector. You then won't need any type conversion.
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| Oct 18, 2019 at 22:52 | comment | added | jsotola | you prevent overflow by adding only 3 bit numbers | |
| Oct 18, 2019 at 22:27 | answer | added | Blair Fonville | timeline score: 1 | |
| Oct 18, 2019 at 22:11 | comment | added | user164324 | @BlairFonville To prevent overflowing. | |
| Oct 18, 2019 at 22:02 | comment | added | Blair Fonville | why do you have a requirement to use the resize function? | |
| Oct 18, 2019 at 21:42 | history | asked | user164324 | CC BY-SA 4.0 |