Timeline for VHDL: Convert std_logic to std_logic_vector
Current License: CC BY-SA 4.0
15 events
| when toggle format | what | by | license | comment | |
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| Apr 18, 2020 at 15:07 | comment | added | Michael Dreher | the nice thing about 2th complement arithmetic is, that the '+' operation doesn't care if the operands are signed or unsigned. | |
| Oct 23, 2019 at 8:28 | comment | added | scary_jeff |
It's bad practice to perform arithmetic on std_logic_vector because the code lines and signals used to implement it give no clue as to whether the operation is supposed to be signed or unsigned. The whole point of a strongly typed language is to avoid this confusion and detect many classes of bug at compile time. Sure you can bypass some of this using std_logic_unsigned, but what if you want signed and unsigned arithmatic in the same file? If you find numeric_std results in excessive casting, you are not using the typing system effectively.
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| Oct 21, 2019 at 0:53 | comment | added | ks0ze | @TonyM, I agree that every tool I have worked with supports std_logic_unsigned. I wouldn't think support would be dropped any time soon due to backwards comparability reasons, but now that the functionality has been rolled into the VHDL standard libraries I could see it happening at some point. Why support two implementations of the same library? | |
| Oct 20, 2019 at 9:43 | comment | added | TonyM | @BlairFonville, that's very true but I value the explanatory nature of the long form, or whatever form that gives most clarity. Though trivial in this short file, engineers reading my files can see and understand the design more clearly. | |
| Oct 20, 2019 at 2:10 | comment | added | Blair Fonville | Just a note: you don’t need to concatenation “0000” to Cin. The std_logic_unsigned library has a + operator overload to add std_logic to std_logic_vector. | |
| Oct 19, 2019 at 21:47 | comment | added | TonyM | @user110971, I think you need to re-examine the reality of the phrase 'non-standard' here. It's an oft-repeated fallacy that's easier to repeat than to assess realistically. As a supplier to large number of defence, avionics, marine, space and medical clients, I've had reliability and repeatability and successful code reviews. Quality of digital design and maintenance matter greatly to me and are examined as such. | |
| Oct 19, 2019 at 21:34 | comment | added | user110971 | @TonyM Well I know about a case wherein the change of an FPGA vendor almost resulted in someone’s death due to the use of non-standard libraries. Avoid good practice at your own peril. | |
| Oct 19, 2019 at 21:30 | comment | added | TonyM | @ks0ze, I'm afraid the 'non-standard library' argument against std_logic_unsigned etc. is as antiquated as it is unrealistic and oft-repeated. That library has been distributed with practically all synthesis and simulation tools reliably for decades. I've used it in every project I've done for very many clients for decades and produced clear, concise, supportable and portable designs without the excessive casting others resort to. It's as valid as the 'so-called' standard libraries and isn't going anywhere. | |
| Oct 19, 2019 at 21:30 | comment | added | user110971 | @ks0ze My above comment was a reply to a now deleted comment, so it seems confusing. Indeed the edited answer now works, but uses non-standard libraries, which is just bad practice. If you want to avoid excessive casting, you should just use Verilog. VHDL is a strongly typed language, which can be really annoying at times. In fact, I do prefer Verilog. See the original answer for the full context of my comment. | |
| Oct 19, 2019 at 20:51 | comment | added | ks0ze | @user110971 this does work but uses std_logic_unsigned, which is a non-standard package. You are correct that in VHDL-2008 the same functionality has been included in the standard library numeric_std_unsigned. | |
| Oct 19, 2019 at 19:51 | history | edited | TonyM | CC BY-SA 4.0 |
Expanded and clarified.
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| Oct 19, 2019 at 19:08 | comment | added | user110971 | It doesn’t work. It is only supported in VHDL-2008, but you must use ieee.numeric_std_unsigned. | |
| Oct 19, 2019 at 18:56 | history | edited | TonyM | CC BY-SA 4.0 |
added 21 characters in body
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| Oct 19, 2019 at 18:56 | comment | added | user110971 | You cannot add std_logic_vectors like that. You need to cast them to a numeric type first. | |
| Oct 19, 2019 at 18:53 | history | answered | TonyM | CC BY-SA 4.0 |