Timeline for Are Tri-state buffers even necessary?
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
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| Nov 14, 2019 at 17:20 | comment | added | Criticizing Israel not allowed | You can. <filler text to make the comment long enough> | |
| Nov 10, 2019 at 18:03 | comment | added | Arseniy | Do I understand that that you try to combine outputs of buffer A and B? What about their inputs? Is they separate from each other or combined? Or may be they combined with outputs (bidirectional bus)? If outputs is not combined with inputs I think you can use AND gate. | |
| Nov 9, 2019 at 22:04 | comment | added | jonk | I could add it, I suppose. I'll keep it short, as I'm not in too much of a state for a long discourse. The sad thing is that almost anything I write has to have context. Which means perhaps drawings here. And that means unavoidable work. It may not happen right away -- an hour? Maybe more? Not sure. | |
| Nov 9, 2019 at 21:58 | comment | added | Trevor Mershon | I think I see what you mean. If your comment was an answer I would call my case closed ;) | |
| Nov 9, 2019 at 21:29 | comment | added | jonk | You'll learn soon enough when you start making stuff. It might be one of those things best learned through experience rather than "book-learned." I could try and list the ways, but I'm not in the mood to write an answer of my own. (By the way, there are also open-collector outputs and these can be simply "wire-OR'd." So that's another approach commonly used. In that case, an AND gate with an open collector output does achieve similar things to a two-quadrant + tri-state buffer output.) | |
| Nov 9, 2019 at 21:13 | comment | added | Trevor Mershon | This does add some clarity, since I only own discrete and SSI parts, but it doesn't explain why I shouldn't use an AND gate instead. | |
| Nov 9, 2019 at 20:46 | comment | added | jonk | If you want more than one functional unit output to share a bus, and especially when you are wiring up an external system using MSI/SSI logic parts, then tri-stating makes sense. You can add additional functional units to the bus without going nuts. You can, of course, require that there be only one "owner" of the bus and design it as a multi-input mux that can source from a variety of functional units. To expand the number of functional units, you'd need to break up a bus and insert another mux (and associated control line.) 6 of one, half dozen of another, in some sense. (Fine with FPGA.) | |
| Nov 9, 2019 at 20:03 | answer | added | pjc50 | timeline score: 2 | |
| Nov 9, 2019 at 19:35 | review | First posts | |||
| Nov 10, 2019 at 0:08 | |||||
| Nov 9, 2019 at 19:33 | history | asked | Trevor Mershon | CC BY-SA 4.0 |