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Impedance Mismatch of LVDS DifferentalDifferential Pairs

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Manos
  • 355
  • 2
  • 11

Impedance Mismatch of LVDS Differental Pairs

A mistake was made when designing a set of mother and daughter PCBs, resulting the daughter board to have its LVDS pairs at ~100Ω differential impedance, while the motherboard ~90Ω. The receiver, which is on the motherboard, is a standard LVDS receiver, with 100Ω termination resistors. Those pairs connect via a dedicated FFC cable. The designs are already at the manufacturer and cancelling the order will cost a lot. What are the chances that the communication will survive this mismatch? The clock of the data transfer is between 300-400 MHz.