Timeline for Why does this Verilog hog down 30 macrocells and hundreds of product terms?
Current License: CC BY-SA 3.0
18 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 11, 2012 at 20:22 | history | edited | Tony Ennis | CC BY-SA 3.0 |
added 6 characters in body
|
| Nov 11, 2012 at 20:09 | comment | added | The Photon | These problems always seem to be totally roadblocked until you find the one clue that breaks them open. ROM in a CPLD is likely to be very resource-hungry...it basically has to be emulated with logic. This design sounds like it might be better suited to a (very small) FPGA than a CPLD...if you get a chance to redesign at that level. One of the newer Altera or Lattice CPLD's (which are really FPGAs with built-in configuration memory) might also be a good fit. | |
| Nov 11, 2012 at 18:07 | vote | accept | Tony Ennis | ||
| Nov 11, 2012 at 18:07 | history | edited | Tony Ennis | CC BY-SA 3.0 |
added 1718 characters in body
|
| Nov 11, 2012 at 16:20 | history | edited | Tony Ennis | CC BY-SA 3.0 |
added 354 characters in body
|
| Nov 11, 2012 at 15:41 | history | edited | Tony Ennis | CC BY-SA 3.0 |
changed logical ORs to Bitwise ORs in the 'assign' EDIT.
|
| Nov 11, 2012 at 15:40 | comment | added | Tony Ennis | @ThePhoton changed the code to use the bitwise OR, no material difference. | |
| Nov 11, 2012 at 15:37 | comment | added | Tony Ennis | @ThePhoton Yep, that was next, heh. I was posting the summary information showing your optimization suggestion was recognized and implemented by ISE/XST. | |
| Nov 11, 2012 at 15:35 | history | edited | Tony Ennis | CC BY-SA 3.0 |
added 568 characters in body
|
| Nov 11, 2012 at 15:28 | comment | added | The Photon |
In the code in your edit, I think you want | instead of ||.
|
|
| Nov 11, 2012 at 15:23 | history | edited | Tony Ennis | CC BY-SA 3.0 |
added 532 characters in body
|
| Nov 11, 2012 at 10:36 | answer | added | Michael Karas | timeline score: 6 | |
| Nov 11, 2012 at 5:13 | answer | added | The Photon | timeline score: 7 | |
| Nov 11, 2012 at 4:45 | comment | added | Tony Ennis | Xilinx's ISE... | |
| Nov 11, 2012 at 4:44 | comment | added | The Photon | What tool are you using? | |
| Nov 11, 2012 at 4:39 | comment | added | Tony Ennis | I don't know how many macrocells the construct should consume. However, considering my project is currently consuming 34 macrocells including those two '1 bit' multiplexors, and that these are a small part of the project, I am surprised by this result. | |
| Nov 11, 2012 at 4:30 | comment | added | vicatcu | doesn't every question mark there effectively imply a multiplexer, and structurally you've cascaded them as well? How many macro-cells did you expect it to take? | |
| Nov 11, 2012 at 4:18 | history | asked | Tony Ennis | CC BY-SA 3.0 |