Timeline for Why does this Verilog hog down 30 macrocells and hundreds of product terms?
Current License: CC BY-SA 3.0
7 events
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| Nov 11, 2012 at 15:43 | comment | added | Tony Ennis | I agree with @ThePhoton completely. I have hosed something. I'm as sure as I can be that this used to work - I didn't even notice the consumption it was so small. Oh well, it's a good excuse to start understanding more of the Summary information. | |
| Nov 11, 2012 at 15:25 | comment | added | The Photon | Nice answer. Let's Tony see just how many product terms it should need to implement this logic. Tony, if you use either Xilinx's boilerplate or Michael's equations, and you are still generating hundreds of product terms, then you need to look for a subtle change somewhere else in your code that might have caused the problem; or else look very carefully at the synthesis log file to see if something is happening that you don't expect. | |
| Nov 11, 2012 at 15:14 | comment | added | Tony Ennis | Thanks, I have implemented it. It did not make a material difference, unfortunately. | |
| Nov 11, 2012 at 14:19 | comment | added | Tony Ennis | Thanks, I will do so. This problem is killing me. I believe it was synthesizing more efficiently previously. And then I Changed Something. /selfbonk | |
| Nov 11, 2012 at 12:28 | history | edited | Michael Karas | CC BY-SA 3.0 |
edited body
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| Nov 11, 2012 at 10:42 | history | edited | Michael Karas | CC BY-SA 3.0 |
added 73 characters in body
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| Nov 11, 2012 at 10:36 | history | answered | Michael Karas | CC BY-SA 3.0 |