Timeline for About transistor biasing and coupling capacitors in ICs
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| May 6, 2020 at 14:57 | comment | added | D.A.S. | Transients require an awareness of where to add Miller Capacitance and time scale of RC | |
| May 6, 2020 at 14:53 | comment | added | D.A.S. | These are all Vt=1.2 and beta =0.02 which is somewhat like k/Rdson tinyurl.com/yb9x2nro | |
| May 6, 2020 at 14:49 | comment | added | D.A.S. | All simulations are digital and time scales have infinite range but only 2k points of depth here. But the true power is precise control of any and all variables which is a bit unreal but random noise can be injected. | |
| May 6, 2020 at 14:37 | comment | added | Circuit fantasist | you are "magician"... Paganini of simulations... What else can I say? I dream of exploring CMOS by varying the thresholds of PMOS and NMOS so that they overlap to various degrees. Accordingly, the output should be "pulled" up and down to see the effect of the overlapping. Can simulations be controlled step-by-step? | |
| May 6, 2020 at 14:18 | comment | added | D.A.S. | The time scale ends up being in "slow motion" as the display of 2k points at some ps, ns, us or ms per sample, unless you choose say 500us per sample or more and slide the simulation speed slider more than 50%. | |
| May 6, 2020 at 14:16 | comment | added | D.A.S. | The left was created by a sequence of Add a plot (later to be Y) , , Add next plot (to be X) , Combine , Choose propertiy X/Y , to get the XY transfer function of combined 2 plots. Now without scales. But can be maximized (autoscale) with trace phosphor memory effects. The reason this feels too detailed is because Plots automatically displays the Vmax and Vmin if those boxes are selected in properties of the trace. Or would can choose Power (watt) etc. | |
| May 6, 2020 at 14:15 | comment | added | D.A.S. | The only missing part is a trigger to this sliding trace, but the time sampling rate can be used under options> time or on each trace for scale | |
| May 6, 2020 at 14:09 | comment | added | D.A.S. | This simulator becomes so fast to use with practise that you can add so much much detail you get to see the big picture of all points at the same time and then vary any parameter with a a pot slider like FET THRESHOLD Vgs on the right. Here I made the Pullup R a variable like a Pot. YOu can also use real Pot but this is much easier to create as you can define the slider limits for improved sensitivity from range reduction. tinyurl.com/yb9glbq2 | |
| May 6, 2020 at 13:45 | comment | added | Circuit fantasist | I had fun with your simulation... but I can't get rid of the feeling of being too detailed... What does the left graphic represent - maybe a transfer characteristic? I would make the voltage divider with a potentiometer... | |
| May 5, 2020 at 5:41 | history | answered | D.A.S. | CC BY-SA 4.0 |