VHDL isn't Verilog
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Error: HDL Compiler : 1660 : Procedural assignment to a non-register big_mant is not permitted, left-hand side should be reg/integer/time/genvar

In the lines wherever I try to do the assignment of value, the above error pops up. Please tell me what's the mistake and guide me with the corrected code snippet.

`timescale 1ns / 1ps

module big_small (


input [3:0] mant_A,
input [3:0] mant_B,
input [3:0] exp_diff,
input exp_diffsig,
input mant_diffsig,
output [3:0] big_mant,
output [3:0] small_mant
);




always@(*)

if (exp_diff == 4'b0000)
begin
big_mant <= (mant_diffsig)? mant_B: mant_A;
small_mant <= (mant_diffsig)? mant_A: mant_B;
end


else
begin
big_mant <= (exp_diffsig)? mant_B: mant_A;
small_mant <= (exp_diffsig)? mant_A: mant_B;
end


endmodule