Timeline for Debounce circuit design in Verilog

Current License: CC BY-SA 4.0

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Jun 17 '20 at 12:14 history edited tim CC BY-SA 4.0
Added test bench and simulation results. Corrected bug in Debounce: if (counter == MAX_COUNT - 1)
Jun 17 '20 at 10:51 history edited tim CC BY-SA 4.0
Changed VHDL operators to Verilog operators in edge detect of Debounce module.
Jun 17 '20 at 1:27 review First posts
Jun 18 '20 at 13:53
Jun 17 '20 at 1:23 history answered tim CC BY-SA 4.0