Timeline for Two slaves on the same I2C bus, both response to address check, one working properly but the other is not
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 22, 2020 at 20:45 | comment | added | muyustan | @jsotola interesting point :) | |
| Aug 22, 2020 at 20:43 | comment | added | jsotola | sometimes, the working module is actually the defective one ... perhaps, both modules are supposed to fail | |
| Aug 22, 2020 at 18:56 | answer | added | bem22 | timeline score: 1 | |
| Aug 22, 2020 at 18:43 | answer | added | Emanuel M | timeline score: 1 | |
| Aug 22, 2020 at 18:33 | history | asked | muyustan | CC BY-SA 4.0 |