Timeline for Via layout for decoupling capacitors
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
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| Aug 25, 2020 at 18:24 | comment | added | w00t | Ah, I now see how rotating the capacitor 90 degrees reduces the inductive loop. Might as well do it anyways to conserve space. Thank you both! | |
| Aug 25, 2020 at 18:23 | vote | accept | w00t | ||
| Aug 25, 2020 at 15:05 | comment | added | The Photon | @w00t, I agree with everything in this answer. That said, at 20 MHz, with ~9 mm between the power and ground pins of the chip, you don't need to worry about 0.01's of mm difference in the placement of your capacitor. | |
| Aug 25, 2020 at 8:14 | comment | added | Puffafish | @w00t The first picture would be fine, but the capacitor could be moved closer in to reduce the inductive loop more. The second picture would also be ok, but the capacitor could be rotated to reduce the loop again. | |
| Aug 25, 2020 at 8:12 | comment | added | w00t | Thank you for the detailed response! To clarify, connecting the vias directly to the IC refers to this type of layout: imgur.com/a/2VYRT19. Would a better via layout for the +5V rails look like this - imgur.com/a/mmYjVXU? This would have the least mutual inductance between vias, and the shortest ground loop for both the IC and the decoupling cap. | |
| Aug 25, 2020 at 7:54 | history | answered | Puffafish | CC BY-SA 4.0 |