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Sep 16, 2020 at 22:58 comment added alex.forencich @supercat many toolchains do provide this feature. Any tools that can do partial reconfiguration theoretically have the ability to do that. Vivado can also do out-of-context synthesis runs for IP cores, but the output of that gets placed and routed along with the rest of the design. I'm pretty sure you can partition/floorplan a design for place and route as well, although I have never tried that myself.
Sep 11, 2020 at 17:27 comment added supercat I wonder how hard or how limiting it would be for a toolchain to provide an option to partition a chip into blocks, each containing a certain subset of the chip's resources, and then allow synthesis to be performed on each block as though it were an entire project, and when synthesizing the whole chip fill in the blocks with their pre-synthesized circuits (so the whole-chip-synthesis step would mainly involve routing the interconnects between the blocks and the outside world).
Sep 10, 2020 at 22:17 comment added supercat Even in the days when linkers were just linkers, they were often very slow. I'd guess it's because they were use the same approaches to link programs that were small enough to be linked in memory at the same time as the linker, as they would use to link much larger programs, and thus have to read every input file while writing a file containing all the symbols, then sort that file, and re-read every input file while combining it with the symbol table to produce the final output.
Sep 10, 2020 at 9:34 comment added Gizmo You should mention that, while it's not the linkers' job to optimize - we do have LTO (Link-Time Optimization). See GCC LTO. MSVC also has this. This can take a considerable amount of time. You'll know when you compile Chromium :') It's even noticeable on smaller projects.
Sep 9, 2020 at 21:22 vote accept gyuunyuu
Sep 9, 2020 at 21:22
Sep 9, 2020 at 21:21 history answered dim CC BY-SA 4.0