Timeline for Understand a counter in VHDL
Current License: CC BY-SA 4.0
17 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Dec 23, 2020 at 14:06 | comment | added | Ben | I cannot judge the coding style, I'm challenged by the fact to understand the coding alongside with the functionality of a counter. But yes, your right in regard that I need basics :) For others coming across this question somewhen maybe, I finally found a good source to look it up in detail with good and short explanations: de.wikibooks.org/wiki/Digitale_Schaltungstechnik/_Flipflop/… Unfortunately, it is not in English but I think with a built-in browser translator it should work relative flawlessly. | |
| Dec 23, 2020 at 13:57 | comment | added | Mitu Raj | While using wait on statement works, I don't recommend it as a good coding style. By the way, looking at your code, I think you should revisit the fundamentals for eg: how to design a D flip-flop in vhdl/verilog. Use ug901 xilinx vivado synthesis guide as the reference to start with (if it's xilinx FPGA). | |
| Dec 23, 2020 at 13:53 | comment | added | Ben | According to the manual I first have to simulate(?) via ghdl but this happens in the terminal and, for me, the only goal is not come up with an error when doing so. Afterwards I use gtkwave. In gtkwave I'm not able to change the load but afaik meanwhile, the meaning of the load is only to start with an arbitrary number, instead of 0? | |
| Dec 23, 2020 at 13:06 | comment | added | po.pe | gtkwave is not a simulator but only a viewer. A simulator would be something like GHDL. What you do in gtkwave is adding all relevant signals to your view and then check how they behave over time. So your clock should alternative with the expected frequency and your output value should show a counter. Altough I'm not sure what you exactly loaded... | |
| Dec 23, 2020 at 12:50 | comment | added | Ben | @po.pe Yes or it seems so. I don't know what gtkwave exactly is but it is given that we shall run it in gtkwave after we found and fixed a bug.. I added the image in the question. I see that edges are rising and falling when the clock is increasing but I cannot really see or learn something there but there is probably a reason for that tool :) | |
| Dec 23, 2020 at 12:49 | comment | added | Ben | @BrianDrummond Yeah, I'm overchallenged with that task already.. sorry, I don't know what to do exactly. I have to build up more basics first, obviously.. | |
| Dec 23, 2020 at 12:47 | history | edited | Ben | CC BY-SA 4.0 |
added img
|
| Dec 23, 2020 at 11:24 | comment | added | user16324 | Pick any major FPGA tool chain, and read their "synthesis style guide" : it contains skeleton examples of the code styles best supported for synthesis. Follow these and you won't go too far wrong. | |
| Dec 22, 2020 at 19:55 | comment | added | po.pe | @Ben can you run the code in a simulator? Maybe seeing what's happening would help understanding... a bit | |
| Dec 22, 2020 at 19:47 | comment | added | user16324 | For a start, what happens if you assert "load" and keep on clocking the counter (while load is still asserted)? | |
| Dec 22, 2020 at 19:39 | vote | accept | Ben | ||
| Dec 22, 2020 at 19:39 | |||||
| Dec 22, 2020 at 19:38 | comment | added | Ben | @po.pe Yep, that's true :) As I wrote, it's part of a modul, the second from around 15 topics. Apparently, they demand too much (for me). However, I would like to learn it nevertheless. | |
| Dec 22, 2020 at 19:36 | comment | added | Ben | @BrianDrummond Really? It's from the modul I'm attending. It's a single course about hardware&software from a state university. | |
| Dec 22, 2020 at 19:26 | comment | added | po.pe | Why did you come across VHDL and what is your background? It seems like you're missing some essential aspects of it... | |
| Dec 22, 2020 at 19:26 | answer | added | po.pe | timeline score: 1 | |
| Dec 22, 2020 at 19:19 | comment | added | user16324 | Where on earth did you find that example? It's awful. | |
| Dec 22, 2020 at 19:11 | history | asked | Ben | CC BY-SA 4.0 |