Here is a link of a simulation:

Link to simulation

The NMOS is connected to the VDD, but when it is turned off we have VSD=0,435 V. Why is the drop not 1,2 V?

The reason I don't understand this is that when the NMOS is off we are not able to attract any electrons from the p-substrate in the NMOS, so how does it not completely shut the current off and we have a voltage drop of 1,2 V, instead of 0,435 V?

When we swap the drain and source in the NMOS the drop will be 1,2 V, why does it then work? Heres another simulation  simluation 2, look at the left case. Here when the two NMOS on top is turned off, they have an intermediate voltage drop, but here it doesn't matter where the drain and souce is?

Here is a link to a Falstad simulation:

Link to simulation 1

The NMOS is connected to the VDD, but when it is turned off we have VSD=0,435 V. Why is the drop not 1,2 V?

The reason I don't understand this is that when the NMOS is off, we are not able to attract any electrons from the p-substrate in the NMOS, so how does it not completely shut the current off and we have a voltage drop of 1,2 V, instead of 0,435 V?

When we swap the drain and source in the NMOS the drop will be 1,2 V, why does it then work?

Here's another simulation:

Link to simulation 2

Look at the left case. Here when the two NMOS on top are turned off, they have an intermediate voltage drop, but here it doesn't matter where the drain and source are?

Here is a link of a simulation:

Link to simulation

The NMOS is connected to the VDD, but when it is turned off we have VSD=0,435 V. Why is the drop not 1,2 V?

The reason I don't understand this is that when the NMOS is off we are not able to attract any electrons from the p-substrate in the NMOS, so how does it not completely shut the current off and we have a voltage drop of 1,2 V, instead of 0,435 V?

When we swap the drain and source in the NMOS the drop will be 1,2 V, why does it then work?

Here is a link of a simulation:

Link to simulation

The NMOS is connected to the VDD, but when it is turned off we have VSD=0,435 V. Why is the drop not 1,2 V?

The reason I don't understand this is that when the NMOS is off we are not able to attract any electrons from the p-substrate in the NMOS, so how does it not completely shut the current off and we have a voltage drop of 1,2 V, instead of 0,435 V?

When we swap the drain and source in the NMOS the drop will be 1,2 V, why does it then work? Heres another simulation simluation 2, look at the left case. Here when the two NMOS on top is turned off, they have an intermediate voltage drop, but here it doesn't matter where the drain and souce is?