Timeline for LVTTL Buffer IC output logic when input is high and not connected to supply voltage
Current License: CC BY-SA 4.0
14 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 9, 2021 at 3:34 | answer | added | saikumarkanikatla | timeline score: 0 | |
| Mar 1, 2021 at 12:55 | comment | added | D.A.S. | Try removing the buffer and add a 100 Ohms or so in series at Tx instead to reduce the ringing from mismatched impedances. Its not a buffer you need | |
| Mar 1, 2021 at 8:51 | comment | added | saikumarkanikatla | Thank you @mkeith. It is confirmed both theoretically(from datasheet) and practically(from physical observation) that this Buffer IC doesn't support the Partial power down. So I want to use an alternate IC which supports the above mentioned feature. I want to save myself with the designing time and manufacturing expenditure by finding a pin compatible IC. | |
| Mar 1, 2021 at 8:32 | history | edited | saikumarkanikatla | CC BY-SA 4.0 |
added 98 characters in body
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| Mar 1, 2021 at 8:17 | comment | added | user57037 | Interfacing IO signals between two IC's which are not powered up at the same time can be pretty tricky. But some buffers support it. The magic words in the data sheet, at least for TI parts are "Partial power off" or "Ioff". Datasheets that mention that are able to maintain all inputs at high impedance when VCC is not present. Also, all outputs will be high impedance and floating. | |
| Mar 1, 2021 at 7:42 | answer | added | Lorenzo Marcantonio | timeline score: 1 | |
| Mar 1, 2021 at 7:20 | comment | added | saikumarkanikatla | @BruceAbbott The input to my system comes from a client device, the cable runs over a length of 1.5 meters. In order to increase the drive strength of these LVTTL signals before giving it to the FPGA, I am using this Buffer IC. | |
| Mar 1, 2021 at 7:14 | comment | added | saikumarkanikatla | Thank you @TonyStewartSunnyskyguyEE75 . But there are no IOs to control the POR. And I have made the output enable signals active default. | |
| Mar 1, 2021 at 7:12 | comment | added | Bruce Abbott | You say that you are using this IC to 'buffer' the signal. Exactly why are you doing this? | |
| Mar 1, 2021 at 5:48 | comment | added | D.A.S. | I don’t understand your interconnections but Pwr on reset low until Vdd detected. | |
| Mar 1, 2021 at 5:44 | comment | added | saikumarkanikatla | Is there any way I can use the same circuitry with some modifications and make the output low till the device is powered on. Or can you suggest me any other buffer IC which suits my application. | |
| Mar 1, 2021 at 5:31 | comment | added | D.A.S. | Not a good idea. the ESD diodes are pulling Vdd up from the input which enables an output driven by your source. The 74ALC family has 25 Ohm driver. never apply signals before power on CMOS. this can cause latch up. | |
| Mar 1, 2021 at 4:28 | review | First posts | |||
| Mar 1, 2021 at 4:43 | |||||
| Mar 1, 2021 at 4:20 | history | asked | saikumarkanikatla | CC BY-SA 4.0 |