Timeline for How to analytically find node voltages in a voltage doubler?
Current License: CC BY-SA 4.0
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| Mar 10, 2021 at 18:01 | comment | added | jonk | @KD9PDP It can be extended, but with now a need to deal with changing the assumptions about a narrow current pulse width. \$C_1\$'s charging period will now be an RC behavior and so will its discharging period. With enough source impedance the voltage across \$C_1\$ becomes increasingly close to a sinusoidal wave (with blunted tops and bottoms due to the diode turn-on action) and the output voltage more like a triangle wave than a sawtooth. The loaded output of your source would look more like a square-wave with tops at the load-current times the source-resistance. | |
| Mar 10, 2021 at 14:29 | comment | added | KD9PDP | There is one question I'm still thinking about though, if the reactance of the first capacitor is much smaller than the source impedance (as in a sound card output), the voltage across C1 might not reach the AC peak, and if the load impedance is on the order of the source impedance, C2 won't reach the 2xDC peak. But your example can be extended to that case as well, thanks! | |
| Mar 10, 2021 at 14:19 | vote | accept | KD9PDP | ||
| Mar 10, 2021 at 14:19 | comment | added | KD9PDP | Bravo! That first assumption was what was screwing me up, but saying D2 conduction is short makes it work! Excellent! And thank you for the design example and simulation. | |
| Mar 9, 2021 at 22:04 | history | answered | jonk | CC BY-SA 4.0 |