Timeline for Is there a microcontroller with zero interrupt jitter?
Current License: CC BY-SA 4.0
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| Aug 23, 2021 at 17:17 | comment | added | user4574 | @schnedan I agree that if data structures can be used that don't require critical sections then that problem goes away. Thanks. the answer was changed to reflect that. Interestingly, it tends to be the older 8-bit processors/MCU like a PIC or AVR that are deterministic. On something like a PIC atomically switching between buffers must be done with care. There is not a way to pull an arbitrary 16-bit pointer out of memory and populate the bank select bits and INDF atomically. The buffers must both either be in the same bank, or same offset in different banks to atomically switch. | |
| Aug 23, 2021 at 10:18 | comment | added | schnedan | " If your interrupt occurs while a critical section is executing then you just created non-deterministic interrupt latency." Thats only relevant if the data is altered in the interrupt. Also you should keep interrupts and such sections short. So if memory is available, e.g. a double-buffer (fifo) can be used, so no disabling of the interrupt is needed and jitter is reduced. | |
| Aug 23, 2021 at 6:28 | comment | added | schnedan | in short: on an deterministic mcu, without caches n stuff, the code and data size in interrupts only add latency, but not jitter. if your mcu has modern features like out of order and caches, every piece of sw, no matter of code and data size has now jitter (but without further thinking about, it should have an upper bound...). | |
| Aug 23, 2021 at 1:39 | history | edited | user4574 | CC BY-SA 4.0 |
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| Aug 23, 2021 at 1:36 | comment | added | user4574 | @schnedan It would be useful if you would elaborated further. If there is any mistake I will amend my answer to avoid misleading any readers. | |
| Aug 22, 2021 at 21:35 | comment | added | schnedan | without elaborating further, "So to sum up, if you want completely deterministic timing you can't use any data structures larger than the processor register size (8, 16, 32, 64 bits) that are also somehow shared with interrupt code" is totally wrong! | |
| Aug 21, 2021 at 4:38 | history | edited | user4574 | CC BY-SA 4.0 |
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| Aug 21, 2021 at 4:32 | history | answered | user4574 | CC BY-SA 4.0 |