Timeline for Does the SPI protocol specify how many clock pulses a master device should send to the slave?
Current License: CC BY-SA 4.0
14 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 10, 2021 at 22:26 | answer | added | jdw | timeline score: 1 | |
| Nov 10, 2021 at 18:57 | comment | added | ilkkachu | "this means that the master implementer needs to know the impl. details of the slave (and all the potential slaves)" -- well, yes, and no. E.g. the SPI hardware on a microcontroller doesn't need to know about all possible slaves, it's usually enough to just have a hardware function for clocking a byte on the wire. (plus buffering for speed maybe) Software can then deal with the particulars of the specific slaves used in the device, it already needs device-specific knowledge of what the data is, so knowing if e.g. a dummy byte needs to be sent is not a huge burden. | |
| Nov 10, 2021 at 10:02 | comment | added | Michael | Some slave devices need a minimum number of bytes or require a “dummy” byte to be sent. | |
| Nov 10, 2021 at 9:00 | history | tweeted | twitter.com/StackElectronix/status/1458358795755737089 | ||
| Nov 10, 2021 at 1:01 | history | became hot network question | |||
| Nov 9, 2021 at 20:56 | comment | added | Sittin Hawk | You need to look at the datasheet of the device you're trying to drive. It has all the rules. In general: follow the protocol as defined in the device's datasheet. Typically the SPI transaction "resets" when the master transitions the slave select from inactive to active, and then a specific number of clocks is sent, according to the datasheet. | |
| Nov 9, 2021 at 18:40 | vote | accept | Martel | ||
| Nov 9, 2021 at 18:18 | answer | added | Justme | timeline score: 7 | |
| Nov 9, 2021 at 17:46 | answer | added | brhans | timeline score: 18 | |
| Nov 9, 2021 at 17:33 | answer | added | awjlogan | timeline score: 17 | |
| Nov 9, 2021 at 17:16 | comment | added | jay | SPI clocks one each for a data bit, so a byte takes 8 clocks. Thus, 4KB x 8 = 32K clock cycles. | |
| Nov 9, 2021 at 17:10 | comment | added | Martel | @jay what do you mean by 'memory cycles'? I understand that they say you can send from 1 byte to 4 KB of data, yet I still don't see how many clock cycles should be sent in total. | |
| Nov 9, 2021 at 17:05 | comment | added | jay | Owe, good question! It seems depending on who calls theirs standard. I found a Wikipedia article, Intel claims their standard is: "This standard supports standard memory cycles with lengths of 1 byte to 4 kilobytes of data." I am not sure why not 4 bits to 1 M bytes. | |
| Nov 9, 2021 at 16:59 | history | asked | Martel | CC BY-SA 4.0 |