Timeline for Intel FPGA Avalon I2C (Master) Core IP: Where are SCL_OUT and SDA_OUT?
Current License: CC BY-SA 4.0
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| Mar 17, 2022 at 2:27 | comment | added | Rodo | Interesting... so the "data out" are actually the output enable signals? Except that they'll be inverted (the data) when driving the tri-state buffer so you get the correct value at the output of the buffer? Wow, I didn't think about that one.... if my thinking is correct that is, is it? | |
| Mar 17, 2022 at 0:45 | history | answered | Justme | CC BY-SA 4.0 |