Timeline for How to divide 50MHz down to 2Hz in VHDL on Xilinx FPGA
Current License: CC BY-SA 3.0
2 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 3, 2021 at 15:50 | comment | added | Benjamin Crawford Ctrl-Alt-Tut | This is not a correct answer for this particular application, as Clocking Wizard cannot generate such a low frequency. | |
| Mar 20, 2013 at 13:50 | history | answered | Arturs Vancans | CC BY-SA 3.0 |