Timeline for PCB panel design
Current License: CC BY-SA 4.0
16 events
| when toggle format | what | by | license | comment | |
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| May 22, 2022 at 10:37 | comment | added | ElectronicsStudent | @Frog Thank you very much! | |
| May 21, 2022 at 6:48 | comment | added | Frog | @ElectronicsStudent I’ve made some panels that will barely support their own weight (one 0.5mm web of FR4 on each side), if you’re ok with that then the danger of damaging the boards during depanelisation will be minimised. My feeling is that anything beyond 0.5mm from the snap-offs should be safe | |
| May 20, 2022 at 20:48 | comment | added | Spehro 'speff' Pefhany | Inner layers has a much better chance, but consider using unplated holes and running traces between them. | |
| May 20, 2022 at 20:43 | comment | added | ElectronicsStudent | @SpehroPefhany I do interprete your answer with a strong focus on the outer layers. I do fully get this. Do you think there will be an issue with the inner Layers peeling out also? To clarify: My idea is to route DUT-tracs for production testing through the mousebites - therefore the plated vias to avoid Copper<-> Edge limit constraints. I am thinking: Maybe it is possible to remove the outer pads but process the via as complete throughhole - without extra cost for buried vias. What is you opinion on this? Thank you very much! | |
| May 20, 2022 at 20:37 | comment | added | ElectronicsStudent | @Frog Currently i am not worried about the panel stability. Due to production equipment the Panel is a X=1, Y=... array so ridgid clamping during SMT and other steps is not an issue. (Not visible on images). Do you think, that damage to the components/joints can occure with a .5mm PCB (4L) ? I know this hard to answer - a educated guess maybe? Thank you in advance | |
| May 20, 2022 at 19:36 | comment | added | Spehro 'speff' Pefhany | Looks like you're using plated-through holes which are going to break in a very messy manner with your traces peeling up and such like. | |
| May 20, 2022 at 19:33 | comment | added | Frog | Can you put the mouse bites (aka stamp holes) in locations where they aren’t close to the components/tracks you’re worried about? The stress caused when depanelising depends on the amount of material left around these holes, so you will want to trade that off against the stability of the panel. | |
| May 20, 2022 at 19:25 | history | edited | ElectronicsStudent | CC BY-SA 4.0 |
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| May 20, 2022 at 19:09 | history | edited | JRE | CC BY-SA 4.0 |
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| May 20, 2022 at 17:41 | history | edited | ElectronicsStudent | CC BY-SA 4.0 |
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| May 19, 2022 at 17:56 | comment | added | ElectronicsStudent | Thank you very much for your response @citizen Every comment and suggestion does help. Do you have experience with this "fine track" stuff? Could you recommend some ideas on "the common pitfalls for novices" like me? | |
| May 19, 2022 at 17:55 | comment | added | ElectronicsStudent | Thank you very much for your response @SpehroPefhany I am planing to use some sort of fixure for the breakaway - just doing the mind games righ now. Regarding the mouse bites: What, in your opinion, is the trouble i am asking for? | |
| May 19, 2022 at 16:51 | history | edited | JYelton | CC BY-SA 4.0 |
Spelling, capitalization, removed unnecessary greeting/thanks (this isn't a forum)
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| May 19, 2022 at 13:37 | comment | added | Spehro 'speff' Pefhany | Normally mouse bites are unplated holes. You’re asking for trouble, IMHO. And if you’re using crude hand depanelizing I’d be more concerned about reliability than yield. But it costs little to try some test panels. | |
| May 19, 2022 at 8:40 | comment | added | citizen | I think you'll be able to answer most of your questions by manufacturing one test panel and trying out all the features you plan to introduce. Having said that though, you can mitigate all your concerns to start off by respecting ALL minimum clearance requirements set by the PCB manufacturer + adding some margin on top of that if your constraints permit it. So, if the manufacturer has an 0.5mm minimum copper to board edge recommendation then you'd want to use that, with some margin on top if you can afford it... my 2cents worth, if it helps ... | |
| May 19, 2022 at 2:19 | history | asked | ElectronicsStudent | CC BY-SA 4.0 |