I found a solution to list all forgotten reset of a design or module. This is possible with the tool called Synplify Pro.

The tool is not free in its standalone version I guess. But it is possible to use it in a free version through Lattice Diamond tool. Lattice Diamond tool uses Synplify Pro for synthesis. It is included in the install. The license is free (to download on Lattice website)

I created a project for my module with Lattice Diamond tool and opened the .srr file generated after synthesis and found the following warning:

@A: CL282 :"C:\test\test\vhdl\counter.vhd":40:4:40:5|Feedback mux created for signal busy. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.

This is a single line for one signal, there are much more in my srr file

I found a solution to list all forgotten resets of a design or module. This is possible with the tool called Synplify Pro.

The tool is not free in its standalone version I guess. But it is possible to use it in a free version through Lattice Diamond tool. Lattice Diamond tool uses Synplify Pro for synthesis. It is included in the install. The license is free (to download on Lattice website)

I created a project for my module with Lattice Diamond tool and opened the .srr file generated after synthesis and found the following warning:

@A: CL282 :"C:\test\test\vhdl\counter.vhd":40:4:40:5|Feedback mux created for signal busy. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.

This is a single line for one signal, there are much more in my srr file.

My resets are asynchronous ones.