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Aug 3, 2022 at 0:42 comment added Andrew Lentvorski While it is true that generator can create 1ns rise times, it comes with limitations (see page 115). Your internal impedance is 50 Ohms. It also has a current limit of 200mA. Implementing both of these will make your simulation much more realistic. However, modeling the load of this circuit at Vout (especially if it's 50 Ohms) is likely to be the biggest thing to make the simulation closer to reality.
Aug 2, 2022 at 16:29 comment added EJE If you could update your post with the suggested (1) Output loading (Capacitor + Resistor); (2) Increasing rise/fall time of Square waves; (3) Combined effect with “1+2”; they would show actual improvements using your initial models. All this would be greatly appreciated.
Aug 2, 2022 at 7:15 comment added Svedberg I actually am using this circuit in laboratory conditions. I'm using this delay generator module (thinksrs.com/downloads/pdfs/manuals/DG645m.pdf) which specifies a rise time of <2 ns or <1 ns, on page viii. Though I agree that this is a pretty unusual situation.
Aug 1, 2022 at 6:56 comment added PStechPaul IMHO, questions like this need to be presented in terms of real world application and intent, versus purely academic and theoretical concepts and curiosity. In this case the 1 nS pulse transitions are unrealistic outside of laboratory conditions, and all sorts of parasitic elements such as capacitance and inductance will have a major effect.
Aug 1, 2022 at 3:14 history edited Dave Tweed
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Aug 1, 2022 at 3:07 vote accept Svedberg
Aug 1, 2022 at 1:59 answer added Andrew Lentvorski timeline score: 6
Aug 1, 2022 at 1:05 comment added DKNguyen Either decrease the parasitic capacitance in the transistor or slow down the edge.
S Aug 1, 2022 at 0:58 review First questions
Aug 1, 2022 at 1:15
S Aug 1, 2022 at 0:58 history asked Svedberg CC BY-SA 4.0