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Timeline for Over-power protection circuit

Current License: CC BY-SA 4.0

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Aug 9, 2022 at 14:45 comment added Power JJ Hi @Verbal Kint, May I have your help?
Aug 8, 2022 at 14:46 comment added Power JJ Hi @Verbit Kint, Excuse me, Just want to check it with you, this document is based on the below conditions to analyze it, which mean is over power right, so I can't use the normal condition to think? in output short circuits, at start-up, or when the optocoupler is destroyed
Aug 8, 2022 at 12:57 comment added Verbal Kint Hi @PowerJJ, the propagation delay could ideally be zero but the converter approaching DCM at high line naturally transmits more power than at low line where it operates in CCM. More power at high line induces more stress on the semis and risks of fire in case of a fault (see limited power test). The compensation should be nonlinear in theory to have a flat characteristic but it's usually enough to build a simple offset.
Aug 8, 2022 at 5:51 comment added Power JJ Hi @Verbal Kint, I read your paper, and have some questions: In an ideal situation, the output power should be the same during the Low Line or High Line, right? If we don't control it, the Low Line and High Line power will have a large gap. 1. What happens if we have a large gap between HL and LL? 2. if we compensate for it, in the ideal situation, no efficiency drop, and the output power at the HL and LL should be the same, but in practice, the efficiency is different in HL and LL, so after the compensation, we sill can see the different power in the HL and LL, is it correct?
Aug 7, 2022 at 20:01 comment added Verbal Kint Hi @PowerJJ, uncompensated means a converter without OPP and compensated means the same converter with OPP turned on.
Aug 7, 2022 at 1:31 comment added Power JJ Hi @Verbal Kint, Thanks. I see. One more question, could you explain the Mathcad figure? What is compensated and uncompensated mean?
Aug 6, 2022 at 17:14 comment added Verbal Kint Hi @PowerJJ, originally, the UC384x had 1 V as a maximum setpoint but it brings losses across the sense resistance. Onsemi has adopted 0.8 V which helps efficiency-wise and I think NXP uses 0.5 V which is even better. The smaller the voltage the best the efficiency but the worse the noise susceptibility of course. It goes into fault if you increase the load current until the setpoint touches the maximum limit of 0.8 V.
Aug 6, 2022 at 16:40 comment added Power JJ Hi @Verbal Kint, Do you mean that when the voltage is a high line, the Vopp is higher (negative), so 0.8+Vopp will be small, and then the current setup point will be reduced? How do determine the 0.8V in the circuit? if we can increase the voltage and we can have more high current. any reason ONSEMI choose 0.8V? From your two figures, I can know the High Line will have a large margin than the Low line, but why it will run into fault? is the transient reason?
Aug 6, 2022 at 12:13 history answered Verbal Kint CC BY-SA 4.0