I migrated project from DE0-Nano to custom board with Altera Cyclone IV EP4CE22E22 (TQFP-144). I don't know if I migrated it correctly since I am not the author of the project and it's first project for Altera I'm working on.

When I try to upload the project to flash of my board, it throws an error:

Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.

I guess there is a problem with hardware since I am able to load the project to DE0-nano. Also I am able to load the project to the fpga's ram.

I'm using Quartus 18.1 and when I googled this error, I found that since Quartus 18.1 till Quartus 19.4 there is a bug causing this error. I tried to install Quartus 21.1 but it seems that Nios II compilation tools are missing so I am not able to rebuild it with the new version. I tried to load project with version 21.1 but compiled with 18.1 with the same error.

MSEL pins are configured to 101 which should be fast active serial but for JTAG programming it does not matter if I understand datasheet right. MSEL needs to be just non floating.

Here is schematic of flash part (using JTAG connector to program - not part of shared schematics)

I wonder where I made a mistake. Do you see any mistake?

I migrated project from DE0-Nano to custom board with Altera Cyclone IV EP4CE22E22 (TQFP-144). I don't know if I migrated it correctly since I am not the author of the project and it's first project for Altera I'm working on.

When I try to upload the project to flash of my board, it throws an error:

Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.

I guess there is a problem with hardware since I am able to load the project to DE0-nano. Also I am able to load the project to the fpga's ram.

I'm using Quartus 18.1 and when I googled this error, I found that since Quartus 18.1 till Quartus 19.4 there is a bug causing this error. I tried to install Quartus 21.1 but it seems that Nios II compilation tools are missing so I am not able to rebuild it with the new version. I tried to load project with version 21.1 but compiled with 18.1 with the same error.

MSEL pins are configured to 101 which should be fast active serial but for JTAG programming it does not matter if I understand datasheet right. MSEL needs to be just non floating.

Here is schematic of flash part (using JTAG connector to program - not part of shared schematics)

I wonder where I made a mistake. Do you see any mistake?